On 01/15/2014 01:05 AM, Michael S. Tsirkin wrote: > On Tue, Jan 14, 2014 at 08:50:54AM -0500, Mike Day wrote: >> >> "Michael S. Tsirkin" <m...@redhat.com> writes: >> >>> On Fri, Jan 10, 2014 at 08:31:36AM -0700, Alex Williamson wrote: >> >>> Short term, just assume 48 bits on x86. >>> >>> We need to figure out what's the limitation on ppc and arm - >>> maybe there's none and it can address full 64 bit range. >>> >>> Cc some people who might know about these platforms. >> >> The document you need is here: >> >> http://goo.gl/fJYxdN >> >> "PCI Bus Binding To: IEEE Std 1275-1994" >> >> The short answer is that Power (OpenFirmware-to-PCI) supports both MMIO >> and Memory mappings for BARs. >> >> Also, both 32-bit and 64-bit BARs are required to be supported. It is >> legal to construct a 64-bit BAR by masking all the high bits to >> zero. Presumably it would be OK to mask the 16 high bits to zero as >> well, constructing a 48-bit address. >> >> Mike >> >> -- >> Mike Day | "Endurance is a Virtue" > > The question was whether addresses such as > 0xfffffffffec00000 can be a valid BAR value on these > platforms, whether it's accessible to the CPU and > to other PCI devices.
On ppc64, the guest address is limited by 60 bits (2Alex: even PA from HPT has the same limit) but there is no actual limit for PCI bus addresses. The actual hardware has some (less than 60 bits but close) limits but since we do not emulate any real PHB in qemu-spapr and do para-virtualization, we do not have to put limits there and BARs like 0xfffffffffec00000 should be allowed (but we do not really expect them to be as big though). -- Alexey
