This is version two of a patchset which makes a start on AArch64
system emulation by tackling system registers.
The major changes here since v1 are that I've added a set of
patches which rework the reginfo struct to use a separate accessfn
rather than having readfn and writenfn possibly return EXCP_UDEF.
This was suggested by Peter Crosthwaite in the previous round and
I think it is a big improvement.
For correct syndrome information the next step will be that
the translate.c/translate-a64.c code passes helper_access_check_cp_reg()
a prototype syndrome so it can eventually be used by the exception
entry code; but I'm still working on the syndrome register support
code, and anyway this series is already pretty long.
Review appreciated, especially for the early patches in the
series and for the accessfn refactoring, so I can start to
feed these patches into target-arm.next.
thanks
-- PMM
Peter Maydell (35):
target-arm: Fix raw read and write functions on AArch64 registers
target-arm/kvm-consts.h: Define QEMU constants for known KVM CPUs
target-arm: Define names for SCTLR bits
target-arm: Restrict check_ap() use of S and R bits to v6 and earlier
target-arm: Remove unused ARMCPUState sr substruct
target-arm: Log bad system register accesses with LOG_UNIMP
target-arm: Add exception level to the AArch64 TB flags
target-arm: A64: Implement store-exclusive for system mode
target-arm: A64: Implement MSR (immediate) instructions
target-arm: Stop underdecoding ARM946 PRBS registers
target-arm: Split cpreg access checks out from read/write functions
target-arm: Convert performance monitor reginfo to accesfn
target-arm: Convert generic timer reginfo to accessfn
target-arm: Convert miscellaneous reginfo structs to accessfn
target-arm: Drop success/fail return from cpreg read and write
functions
target-arm: Remove unnecessary code now read/write fns can't fail
target-arm: Remove failure status return from read/write_raw_cp_reg
target-arm: Fix incorrect type for value argument to write_raw_cp_reg
target-arm: A64: Make cache ID registers visible to AArch64
target-arm: Implement AArch64 CurrentEL sysreg
target-arm: Implement AArch64 MIDR_EL1
target-arm: Implement AArch64 DAIF system register
target-arm: Implement AArch64 cache invalidate/clean ops
target-arm: Implement AArch64 TLB invalidate ops
target-arm: Implement AArch64 dummy MDSCR_EL1
target-arm: Implement AArch64 memory attribute registers
target-arm: Implement AArch64 SCTLR_EL1
target-arm: Implement AArch64 TCR_EL1
target-arm: Implement AArch64 VBAR_EL1
target-arm: Implement AArch64 TTBR*
target-arm: Implement AArch64 MPIDR
target-arm: Implement AArch64 generic timers
target-arm: Implement AArch64 ID and feature registers
target-arm: Implement AArch64 dummy breakpoint and watchpoint
registers
target-arm: Implement AArch64 OSLAR_EL1 sysreg as WI
hw/arm/pxa2xx.c | 38 +-
hw/arm/pxa2xx_pic.c | 11 +-
target-arm/cpu-qom.h | 10 +
target-arm/cpu.c | 12 +-
target-arm/cpu.h | 153 +++++--
target-arm/cpu64.c | 1 +
target-arm/helper.c | 1093 +++++++++++++++++++++++++++-----------------
target-arm/helper.h | 3 +
target-arm/kvm-consts.h | 16 +-
target-arm/op_helper.c | 65 ++-
target-arm/translate-a64.c | 119 ++++-
target-arm/translate.c | 28 +-
12 files changed, 1025 insertions(+), 524 deletions(-)
--
1.8.5
