On 5 March 2014 15:01, alvise rigo <a.r...@virtualopensystems.com> wrote: > So, if the processor does not start in AArch64 mode, we only add the AArch32 > version of the ARM_CP_STATE_BOTH register to the hashtable, otherwise > nothing changes and we add the two views of the register.
Yes, I think if we want TCG<->KVM migration we're going to have to do something like this. It introduces complication for reset handling, though -- at the moment the aarch64 view handles reset and the aarch32 view does not. We'd need to add (back) reset information in the aarch32 views, and also raw read/write functions if needed. > This approach works only > if all the 64bit CPUs will always start in 64 bit mode. You should be checking for whether the CPU has the AARCH64 feature, which would fix that nit. > In my opinion, other solutions would require to revisit the idea of > ARM_CP_STATE_BOTH in favour of distinct definitions of the registers with > multiple views (like VBAR for AArch32 and VBAR_EL1 for AArch64). ARM_CP_STATE_BOTH is purely a shorthand to avoid having to write out two definitions when they'd be virtually the same. I don't think it adds any extra complexity that isn't already present for registers that have split definitions. In fact the split-definition registers are trickier because you end up needing all of (1) aarch64 view (2) aarch32-in-aarch64-cpu view (3) aarch32 view, which is pretty ugly. thanks -- PMM
