On Mon, 17 Mar 2014, Andreas Färber wrote:
In earlier times QEMU did not properly support multiple PCI bus domains.
Some code in
http://git.qemu.org/?p=qemu.git;a=blob;f=hw/pci-host/uninorth.c;h=e72fe2a70b954bf5675ad0c8735fea6bad665be6;hb=HEAD
is #if 0'ed out that you should take a look at.
I've seen these #if 0'ed parts but just enabling them does not seem to be
enough. I don't know enough about how should all this work and found no
documentation or examples to follow so I hope someone can explain what it
takes to create two pci buses (so devices added to the first get
0:dev:func and those added to the second get 1:dev:func addresses) and
these busses have their Cfg/IO/MMIO space mapped to different addresses.
The patch I came up with so far did not work. The pci buses and memory map
from the dumps I've seen should look like this:
0000:00:0b.0 Host bridge [0600]: Apple Computer Inc. UniNorth AGP [106b:0020]
0000:00:10.0 VGA compatible controller [0300]: ATI Technologies Inc Radeon R200
QL [Radeon 8500 LE] [1002:514c]
0001:10:0b.0 Host bridge [0600]: Apple Computer Inc. UniNorth PCI [106b:001f]
0001:10:0d.0 PCI bridge [0604]: Digital Equipment Corporation DECchip 21154
[1011:0026] (rev 05)
0001:11:07.0 Unassigned class [ff00]: Apple Computer Inc. KeyLargo Mac I/O
[106b:0022] (rev 02)
corresponding to this openfirmware tree:
ff8721c0: /pci@f0000000
ff898cd0: /uni-north-agp@b
ff898f40: /ATY,Rage128Ps@10
ff873268: /pci@f2000000
ff8742d8: /pci-bridge@d
ff876368: /mac-io@7
and the memory mapping is:
80000000-8fffffff : /pci@f2000000
80000000-800fffff : PCI Bus 0001:11
80000000-8007ffff : 0001:11:07.0
80000000-8007ffff : 0.80000000:mac-io
90000000-9fffffff : /pci@f0000000
90000000-9000ffff : 0000:00:10.0
90000000-9000ffff : radeonfb mmio
f1000000-f1ffffff : /pci@f0000000
f3000000-f3ffffff : /pci@f2000000
I had investigated that some time ago based on a G4 in our office and
might be able to revive some patches... Please keep me CC'ed.
If you have any info/patches for this they are very welcome.
Regards,
BALATON Zoltan
