Am 19.03.2014 22:04, schrieb Richard Henderson: > Ping? This is a significant TCG code size regression > for ARM, AArch64, and Sparc hosts. It helps x86 too, > though that's not as severe.
Sorry, applied to qom-cpu now: https://github.com/afaerber/qemu-cpu/commits/qom-cpu How did you find this? Was there some assertion on one target, or do you have some analysis code that you could share? Thanks, Andreas > > > r~ > > On 03/14/2014 03:30 PM, Richard Henderson wrote: >> Reverse an increase in the size of generated code. >> >> Cc: Andreas Färber <afaer...@suse.de> >> Signed-off-by: Richard Henderson <r...@twiddle.net> >> --- >> include/qom/cpu.h | 7 ++++++- >> 1 file changed, 6 insertions(+), 1 deletion(-) >> >> diff --git a/include/qom/cpu.h b/include/qom/cpu.h >> index 06ee263..f99885a 100644 >> --- a/include/qom/cpu.h >> +++ b/include/qom/cpu.h >> @@ -227,7 +227,6 @@ struct CPUState { >> bool stop; >> bool stopped; >> volatile sig_atomic_t exit_request; >> - volatile sig_atomic_t tcg_exit_req; >> uint32_t interrupt_request; >> int singlestep_enabled; >> int64_t icount_extra; >> @@ -272,6 +271,12 @@ struct CPUState { >> } icount_decr; >> uint32_t can_do_io; >> int32_t exception_index; /* used by m68k TCG */ >> + >> + /* Note that this is accessed at the start of every TB via a negative >> + offset from AREG0. Leave this field at the end so as to make the >> + (absolute value) offset as small as possible. This reduces code >> + size, especially for hosts without large memory offsets. */ >> + volatile sig_atomic_t tcg_exit_req; >> }; >> >> QTAILQ_HEAD(CPUTailQ, CPUState); >> > > -- SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
