> Yes, but I think how you program your host to pci bridge is platform specific, > the standard (mostly) applies to what happens below the bridge. There's > no real standard for how PCI host bridge is connected to processor > AFAIK, it's by luck we can share code there at all.
Well, yes and no ... there's a standard on how a PCI host bridge is connected in the sense that how normal MMIO accesses go through in term of endianness is well defined. How you actually issue config space cycles is a property of a given bridge. How you issue IO cycles as well in fact. Cheers, Ben.
