On 4/6/2014 3:55 PM, Alexander Graf wrote:
<snip>
> @@ -806,6 +838,10 @@ clk_setup_cb cpu_ppc_tb_init (CPUPPCState *env, uint32_t
> freq)
> tb_env = g_malloc0(sizeof(ppc_tb_t));
> env->tb_env = tb_env;
> tb_env->flags = PPC_DECR_UNDERFLOW_TRIGGERED;
> + if (env->insns_flags & PPC_SEGMENT_64B) {
> + /* All Book3S 64bit CPUs implement level based DEC logic */
> + tb_env->flags |= PPC_DECR_UNDERFLOW_LEVEL;
> + }
> /* Create new timer */
> tb_env->decr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_ppc_decr_cb,
> cpu);
> if (0) {
Equating Book3S with PPC_SEGMENT_64B is clever ... is it too clever?
Especially since
the SLB Bridge is in the phased-out category and consequently we should expect
future
Book3S implementations to not support this instruction category.
