On 19 March 2014 21:13, Peter Maydell <peter.mayd...@linaro.org> wrote: > XScale defines some implementation-specific coprocessor registers > for doing cache lockdown operations. Since QEMU doesn't model a > cache no proper implementation is possible, but NOP out the > registers so that guest code like u-boot that tries to use them > doesn't crash. > > Reported-by: <pr...@centrum.cz> > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> > --- > target-arm/helper.c | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) > > diff --git a/target-arm/helper.c b/target-arm/helper.c > index 55077ed..7d99236 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -1525,6 +1525,21 @@ static const ARMCPRegInfo xscale_cp_reginfo[] = { > .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW, > .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr), > .resetvalue = 0, }, > + /* XScale specific cache-lockdown: since we have no cache we NOP these > + * and hope the guest does not really rely on cache behaviour. > + */ > + { .name = "XSCALE_LOCK_ICACHE_LINE", > + .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, > + .access = PL1_W, .type = ARM_CP_NOP }, > + { .name = "XSCALE_UNLOCK_ICACHE", > + .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, > + .access = PL1_W, .type = ARM_CP_NOP }, > + { .name = "XSCALE_DCACHE_LOCK", > + .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 0, > + .access = PL1_RW, .type = ARM_CP_NOP }, > + { .name = "XSCALE_UNLOCK_DCACHE", > + .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 1, > + .access = PL1_W, .type = ARM_CP_NOP }, > REGINFO_SENTINEL > };
Ping? In the absence of any review or test comments I'll put this in target-arm.next... thanks -- PMM