On Tue, May 6, 2014 at 4:08 PM, Edgar E. Iglesias <edgar.igles...@gmail.com> wrote: > From: "Edgar E. Iglesias" <edgar.igles...@xilinx.com> > > Signed-off-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>
Same as last patch, Otherwise: Reviewed-by: Peter Crosthwaite <peter.crosthwa...@xilinx.com> > --- > target-arm/helper.c | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/target-arm/helper.c b/target-arm/helper.c > index 8efc340..65daeaf 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -2091,6 +2091,19 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = { > REGINFO_SENTINEL > }; > > +static const ARMCPRegInfo v8_el3_cp_reginfo[] = { > + { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64, > + .type = ARM_CP_NO_MIGRATE, > + .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1, > + .access = PL3_RW, > + .fieldoffset = offsetof(CPUARMState, elr_el[ELR_EL_IDX(3)]) }, > + { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64, > + .type = ARM_CP_NO_MIGRATE, > + .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0, > + .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[7]) > }, > + REGINFO_SENTINEL > +}; > + > static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, > uint64_t value) > { > @@ -2338,6 +2351,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) > if (arm_feature(env, ARM_FEATURE_EL2)) { > define_arm_cp_regs(cpu, v8_el2_cp_reginfo); > } > + if (arm_feature(env, ARM_FEATURE_EL3)) { > + define_arm_cp_regs(cpu, v8_el3_cp_reginfo); > + } > } > if (arm_feature(env, ARM_FEATURE_MPU)) { > /* These are the MPU registers prior to PMSAv6. Any new > -- > 1.8.3.2 > >