On 6 May 2014 07:08, Edgar E. Iglesias <edgar.igles...@gmail.com> wrote: > From: "Edgar E. Iglesias" <edgar.igles...@xilinx.com> > > Signed-off-by: Edgar E. Iglesias <edgar.igles...@xilinx.com> > --- > target-arm/helper.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/target-arm/helper.c b/target-arm/helper.c > index 2406058..6e3f5fa 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -2088,6 +2088,11 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = { > .type = ARM_CP_NO_MIGRATE, > .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0, > .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[6]) > }, > + { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64, > + .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0, > + .access = PL2_RW, .writefn = vbar_write, > + .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[1]), > + .resetvalue = 0 }, > REGINFO_SENTINEL > };
ARM ARM says that if EL2 isn't implemented then this register should be RES0 from EL3 (ie not UNDEF). thanks -- PMM