after running some OBP/forth tests on a real SS-20 I must say that most of our (especially my) speculations were wrong, as well as what is written in http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt :
1. SS-20 may loose interrupts. At least if a timer interrupt was lowered while still being masked, it is not triggered when enabled. 2. Neither masking, nor unmasking interrupt clears pending bits in the status register. NCR89C105.txt claims it should, but Sun4M_SystemArchitecture_edited2.pdf doesn't. I guess the later one is more reliable. -- Regards, Artyom Tarasenko solaris/sparc under qemu blog: http://tyom.blogspot.com/