The size and register information are encoded into the reserve_info field of CPU state in the store conditional translation code. Specifically, the size is shifted left by 5 bits (see target-ppc/translate.c gen_conditional_store).
The user-mode store conditional code erroneously extracts the size by ANDing with a 4 bit mask; this breaks if size >= 16. Eliminate the mask to make the extraction of size mirror its encoding. Signed-off-by: Tom Musta <tommu...@gmail.com> --- V4: new patch. linux-user/main.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/linux-user/main.c b/linux-user/main.c index c5668af..d7609f7 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -1497,7 +1497,7 @@ static int do_store_exclusive(CPUPPCState *env) segv = 1; } else { int reg = env->reserve_info & 0x1f; - int size = (env->reserve_info >> 5) & 0xf; + int size = env->reserve_info >> 5; int stored = 0; if (addr == env->reserve_addr) { -- 1.7.1