ARM ARM v7 specifies SBOP/SBZP bits for v5/v6/v7. This patch
sets these bits on every sctlr_write(). In ARMv8 most of them are
RES0/RES1.
Signed-off-by: Fabian Aggeler <aggel...@ethz.ch>
---
Previously part of TZ patchset but now includes handling for SBOP/SBZP
bits in ARMv5/v6/v7. Not sure whether using the SCTLR_* macros makes
it less readable than without them.
target-arm/helper.c | 37 +++++++++++++++++++++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 10b965e..443337a 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2234,6 +2234,43 @@ static void sctlr_write(CPUARMState *env, const
ARMCPRegInfo *ri,
return;
}
+ if (arm_feature(env, ARM_FEATURE_V8)) {
+ /* Lots of bits are now RES0/RES1 */
+ } else if (arm_feature(env, ARM_FEATURE_V7)) {
+ /* In ARMv7 set bits to zero/one as follows
+ * RAO/SBOP: [23:22], [18], [16], [6], [4:3]
+ * UNK/SBZP or RAZ/SBZP: [31], [26], [15], [9:7]
+ */
+ value |= SCTLR_XP | SCTLR_U |
+ SCTLR_nTWE | SCTLR_nTWI | SCTLR_L |
+ SCTLR_P | SCTLR_W;
+ value &= ~((1U << 31) | SCTLR_L2 | SCTLR_L4 |
+ SCTLR_R | SCTLR_S | SCTLR_B);
+ } else if (arm_feature(env, ARM_FEATURE_V6K)) {
+ /* In ARMv6K set bits to zero/one as follows
+ * RAO/SBOP: [18], [16], [6:4]
+ * UNK/SBZP or RAZ/SBZP: [31], [20:19], [10]
+ */
+ value |= SCTLR_IT | SCTLR_DT |
+ SCTLR_L | SCTLR_D | SCTLR_P;
+ value &= ~((1U << 31) | SCTLR_WXN | SCTLR_F);
+ } else if (arm_feature(env, ARM_FEATURE_V6)) {
+ /* In ARMv6 set bits to zero/one as follows
+ * RAO/SBOP: [18], [16], [6:4]
+ * UNK/SBZP or RAZ/SBZP: [31], [29:28], [20:19], [17], [10]
+ */
+ value |= SCTLR_IT | SCTLR_DT |
+ SCTLR_L | SCTLR_D | SCTLR_P;
+ value &= ~((1U << 31) |
+ SCTLR_AFE | SCTLR_TRE |
+ SCTLR_ST | SCTLR_WXN |
+ SCTLR_HA |
+ SCTLR_F);
+ } else {
+ /* Bits [31:16] are UNK/SBZP in ARMv4/ARMv5 */
+ value &= 0x0000ffff;
+ }
+
env->cp15.c1_sys = value;
/* ??? Lots of these bits are not implemented. */
/* This may enable/disable the MMU, so do a TLB flush. */
--
1.8.3.2
