Add instructions of SBC and SBRN opcode format. Signed-off-by: Bastian Koppelmann <kbast...@mail.uni-paderborn.de> --- target-tricore/translate.c | 45 ++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 44 insertions(+), 1 deletion(-)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c index f32e1d1..69d99d3 100644 --- a/target-tricore/translate.c +++ b/target-tricore/translate.c @@ -284,6 +284,7 @@ static inline void gen_branch_condi(DisasContext *ctx, int cond, TCGv r1, static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1, int r2 , int32_t constant , int32_t offset) { + TCGv temp; switch (opc) { /* SB-format jumps */ @@ -302,6 +303,26 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, case OPC1_16_SB_JNZ: gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], 0, offset); break; +/* SBC-format jumps */ + case OPC1_16_SBC_JEQ: + gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], constant, offset); + break; + case OPC1_16_SBC_JNE: + gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], constant, offset); + break; +/* SBRN-format jumps */ + case OPC1_16_SBRN_JZ_T: + temp = tcg_temp_new(); + tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant); + gen_branch_condi(ctx, TCG_COND_NE, temp, 0x1 << constant, offset); + tcg_temp_free(temp); + break; + case OPC1_16_SBRN_JNZ_T: + temp = tcg_temp_new(); + tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant); + gen_branch_condi(ctx, TCG_COND_EQ, temp, 0x1 << constant, offset); + tcg_temp_free(temp); + break; default: printf("Branch Error at %x\n", ctx->pc); } @@ -626,7 +647,29 @@ static void decode_16Bit_opc(CPUTRICOREState *env, DisasContext *ctx) address = sign_extend(MASK_OP_SB_DISP8(ctx->opcode), 7); gen_compute_branch(ctx, op1, 0, 0, 0, address); break; - } +/* SBC-format */ + case OPC1_16_SBC_JEQ: + address = MASK_OP_SBC_DISP4(ctx->opcode); + const16 = sign_extend(MASK_OP_SBC_CONST4(ctx->opcode), 3); + gen_compute_branch(ctx, op1, 0, 0, const16, address); + break; + case OPC1_16_SBC_JNE: + address = MASK_OP_SBC_DISP4(ctx->opcode); + const16 = sign_extend(MASK_OP_SBC_CONST4(ctx->opcode), 3); + gen_compute_branch(ctx, op1, 0, 0, const16, address); + break; +/* SBRN-format */ + case OPC1_16_SBRN_JNZ_T: + address = MASK_OP_SBRN_DISP4(ctx->opcode); + const16 = MASK_OP_SBRN_N(ctx->opcode); + gen_compute_branch(ctx, op1, 0, 0, const16, address); + break; + case OPC1_16_SBRN_JZ_T: + address = MASK_OP_SBRN_DISP4(ctx->opcode); + const16 = MASK_OP_SBRN_N(ctx->opcode); + gen_compute_branch(ctx, op1, 0, 0, const16, address); + break; + } } static void decode_32Bit_opc(CPUTRICOREState *env, DisasContext *ctx) -- 2.0.1