On 07/07/2014 11:13 AM, Bastian Koppelmann wrote: > + case OPC1_16_SSR_ST_B: > + r1 = MASK_OP_SSR_S1(ctx->opcode); > + r2 = MASK_OP_SSR_S2(ctx->opcode); > + temp = tcg_temp_new(); > + tcg_gen_andi_tl(temp, cpu_gpr_d[r1], 0xff); > + tcg_gen_qemu_st8(temp, cpu_gpr_a[r2], ctx->mem_idx); > + tcg_temp_free(temp);
The andi is just silly. Of course the st8 will only examine the low 8 bits. Likewise for the _H insns. r~
