On 28 July 2014 23:52, Aurelien Jarno <aurel...@aurel32.net> wrote: > On Mon, Jul 28, 2014 at 11:34:30PM +0100, Peter Maydell wrote: >> On 28 July 2014 23:32, Aurelien Jarno <aurel...@aurel32.net> wrote: >> > On Mon, Jul 28, 2014 at 11:01:02PM +0100, Peter Maydell wrote: >> >> This may be true, but the TCG README doesn't define negative >> >> lengths as being "unspecified behaviour" (ie guaranteed to at >> >> least not crash even if the result isn't specified), and in fact the >> >> implementation of tcg_gen_deposit will assert on negative lengths. >> >> We shouldn't implement guest unpredictable cases as "crash QEMU". >> > >> > Well I tried this code under QEMU, and it clearly doesn't crash. It >> > seems the assert are not enabled with the default configuration options. >> >> Try --enable-debug... > > That's my point, it's only in debug mode, not in the default > configuration.
Debug builds are pretty common though, it's not exactly something obscure like "only crashes on SPARC hosts". >> > That said I agree it's something to avoid, but I don't think triggering >> > a RI exception is the thing to do (even if it is correct according the >> > MIPS ISA manual) when real silicon output a random result instead. >> >> Yes, you could emit code to do that instead if you like. > > When I said random, it didn't say in the sense of random generator, but > in the sense a result that might depend on the input value and the > silicon implementation. It would be silly to emit code just for that, > but it would be smart for example to skip the deposit op in that case > instead of triggering an exception. That's what I had in mind, yes. thanks -- PMM