Added MSI-X support for qtest PCI.
Added MSI-X support for virtio-pci.
Added MSI-X test case in virtio-blk-test.
Signed-off-by: Marc Marí <marc.mari.barc...@gmail.com>
---
tests/libqos/pci.c | 110 ++++++++++++++++++++++++-
tests/libqos/pci.h | 10 +++
tests/libqos/virtio-pci.c | 145 ++++++++++++++++++++++++++++-----
tests/libqos/virtio-pci.h | 17 ++++
tests/libqos/virtio.c | 17 +++-
tests/libqos/virtio.h | 11 ++-
tests/virtio-blk-test.c | 197 +++++++++++++++++++++++++++++++++++++--------
7 files changed, 447 insertions(+), 60 deletions(-)
diff --git a/tests/libqos/pci.c b/tests/libqos/pci.c
index c9a0b91..82b487d 100644
--- a/tests/libqos/pci.c
+++ b/tests/libqos/pci.c
@@ -15,8 +15,6 @@
#include "hw/pci/pci_regs.h"
#include <glib.h>
-#include <stdio.h>
-
void qpci_device_foreach(QPCIBus *bus, int vendor_id, int device_id,
void (*func)(QPCIDevice *dev, int devfn, void *data),
void *data)
@@ -75,6 +73,114 @@ void qpci_device_enable(QPCIDevice *dev)
qpci_config_writew(dev, PCI_COMMAND, cmd);
}
+uint8_t qpci_find_capability(QPCIDevice *dev, uint8_t id)
+{
+ uint8_t cap;
+ uint8_t addr = qpci_config_readb(dev, PCI_CAPABILITY_LIST);
+
+ do {
+ cap = qpci_config_readb(dev, addr);
+ if (cap != id) {
+ addr = qpci_config_readb(dev, addr+PCI_CAP_LIST_NEXT);
+ }
+ } while (cap != id && addr != 0);
+
+ return addr;
+}
+
+void qpci_msix_enable(QPCIDevice *dev)
+{
+ uint8_t addr;
+ uint16_t val;
+ uint32_t table;
+ uint8_t bir_table;
+ uint8_t bir_pba;
+ void *offset;
+
+ addr = qpci_find_capability(dev, PCI_CAP_ID_MSIX);
+ g_assert_cmphex(addr, !=, 0);
+
+ val = qpci_config_readw(dev, addr+PCI_MSIX_FLAGS);
+ qpci_config_writew(dev, addr+PCI_MSIX_FLAGS, val | PCI_MSIX_FLAGS_ENABLE);
+
+ table = qpci_config_readl(dev, addr+PCI_MSIX_TABLE);
+ bir_table = table & PCI_MSIX_FLAGS_BIRMASK;
+ offset = qpci_iomap(dev, bir_table);
+ dev->msix_table = offset+(table & ~PCI_MSIX_FLAGS_BIRMASK);
+
+ table = qpci_config_readl(dev, addr+PCI_MSIX_PBA);
+ bir_pba = table & PCI_MSIX_FLAGS_BIRMASK;
+ if (bir_pba != bir_table) {
+ offset = qpci_iomap(dev, bir_pba);
+ }
+ dev->msix_pba = offset+(table & ~PCI_MSIX_FLAGS_BIRMASK);
+
+ g_assert(dev->msix_table != NULL);
+ g_assert(dev->msix_pba != NULL);
+ dev->msix_enabled = true;
+}
+
+void qpci_msix_disable(QPCIDevice *dev)
+{
+ uint8_t addr;
+ uint16_t val;
+
+ g_assert(dev->msix_enabled);
+ addr = qpci_find_capability(dev, PCI_CAP_ID_MSIX);
+ g_assert_cmphex(addr, !=, 0);
+ val = qpci_config_readw(dev, addr+PCI_MSIX_FLAGS);
+ qpci_config_writew(dev, addr+PCI_MSIX_FLAGS, val & ~PCI_MSIX_FLAGS_ENABLE);
+
+ qpci_iounmap(dev, dev->msix_table);
+ qpci_iounmap(dev, dev->msix_pba);
+ dev->msix_enabled = 0;
+ dev->msix_table = NULL;
+ dev->msix_pba = NULL;
+}
+
+bool qpci_msix_pending(QPCIDevice *dev, uint16_t entry)
+{
+ uint32_t pba_entry;
+ uint8_t bit_n = entry % 32;
+ void *addr = dev->msix_pba + (entry/32) * PCI_MSIX_ENTRY_SIZE/4;
+
+ g_assert(dev->msix_enabled);
+ pba_entry = qpci_io_readl(dev, addr);
+ qpci_io_writel(dev, addr, pba_entry & ~(1 << bit_n));
+ return (pba_entry & (1 << bit_n)) != 0;
+}
+
+bool qpci_msix_masked(QPCIDevice *dev, uint16_t entry)
+{
+ uint8_t addr;
+ uint16_t val;
+ void *vector_addr = dev->msix_table + (entry * PCI_MSIX_ENTRY_SIZE);
+
+ g_assert(dev->msix_enabled);
+ addr = qpci_find_capability(dev, PCI_CAP_ID_MSIX);
+ g_assert_cmphex(addr, !=, 0);
+ val = qpci_config_readw(dev, addr+PCI_MSIX_FLAGS);
+
+ if (val & PCI_MSIX_FLAGS_MASKALL) {
+ return true;
+ } else {
+ return (qpci_io_readl(dev, vector_addr + PCI_MSIX_ENTRY_VECTOR_CTRL)
+ & PCI_MSIX_ENTRY_CTRL_MASKBIT) !=
0;
+ }
+}
+
+uint16_t qpci_msix_table_size(QPCIDevice *dev)
+{
+ uint8_t addr;
+ uint16_t control;
+
+ addr = qpci_find_capability(dev, PCI_CAP_ID_MSIX);
+ g_assert_cmphex(addr, !=, 0);
+
+ control = qpci_config_readw(dev, addr+PCI_MSIX_FLAGS);
+ return (control & PCI_MSIX_FLAGS_QSIZE) + 1;
+}
+
uint8_t qpci_config_readb(QPCIDevice *dev, uint8_t offset)
{
return dev->bus->config_readb(dev->bus, dev->devfn, offset);
diff --git a/tests/libqos/pci.h b/tests/libqos/pci.h
index 3439431..decf5f6 100644
--- a/tests/libqos/pci.h
+++ b/tests/libqos/pci.h
@@ -14,6 +14,7 @@
#define LIBQOS_PCI_H
#include <stdint.h>
+#include "libqtest.h"
#define QPCI_DEVFN(dev, fn) (((dev) << 3) | (fn))
@@ -49,6 +50,9 @@ struct QPCIDevice
{
QPCIBus *bus;
int devfn;
+ bool msix_enabled;
+ void *msix_table;
+ void *msix_pba;
};
void qpci_device_foreach(QPCIBus *bus, int vendor_id, int device_id,
@@ -57,6 +61,12 @@ void qpci_device_foreach(QPCIBus *bus, int vendor_id, int
device_id,
QPCIDevice *qpci_device_find(QPCIBus *bus, int devfn);
void qpci_device_enable(QPCIDevice *dev);
+uint8_t qpci_find_capability(QPCIDevice *dev, uint8_t id);
+void qpci_msix_enable(QPCIDevice *dev);
+void qpci_msix_disable(QPCIDevice *dev);
+bool qpci_msix_pending(QPCIDevice *dev, uint16_t entry);
+bool qpci_msix_masked(QPCIDevice *dev, uint16_t entry);
+uint16_t qpci_msix_table_size(QPCIDevice *dev);
uint8_t qpci_config_readb(QPCIDevice *dev, uint8_t offset);
uint16_t qpci_config_readw(QPCIDevice *dev, uint8_t offset);
diff --git a/tests/libqos/virtio-pci.c b/tests/libqos/virtio-pci.c
index 184c430..acf785a 100644
--- a/tests/libqos/virtio-pci.c
+++ b/tests/libqos/virtio-pci.c
@@ -16,6 +16,9 @@
#include "libqos/malloc.h"
#include "libqos/malloc-pc.h"
+#include <stdio.h>
+#include <inttypes.h>
+
#include "hw/pci/pci_regs.h"
typedef struct QVirtioPCIForeachData {
@@ -35,6 +38,8 @@ static QVirtioPCIDevice
*qpcidevice_to_qvirtiodevice(QPCIDevice *pdev)
qpci_config_readw(vpcidev->pdev, PCI_SUBSYSTEM_ID);
}
+ vpcidev->config_msix_entry = -1;
+
return vpcidev;
}
@@ -111,10 +116,45 @@ static void qvirtio_pci_set_status(QVirtioDevice *d,
uint8_t status)
qpci_io_writeb(dev->pdev, dev->addr + QVIRTIO_DEVICE_STATUS, status);
}
-static uint8_t qvirtio_pci_get_isr_status(QVirtioDevice *d)
+static bool qvirtio_pci_get_queue_isr_status(QVirtioDevice *d, QVirtQueue *vq)
+{
+ QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
+ QVirtQueuePCI *vqpci = (QVirtQueuePCI *)vq;
+ uint32_t data;
+
+ if (dev->pdev->msix_enabled) {
+ g_assert_cmpint(vqpci->msix_entry, !=, -1);
+ if (qpci_msix_masked(dev->pdev, vqpci->msix_entry)) {
+ /* No ISR checking should be done if masked, but read anyway */
+ return qpci_msix_pending(dev->pdev, vqpci->msix_entry);
+ } else {
+ data = readl(vqpci->msix_addr);
+ writel(vqpci->msix_addr, 0);
+ return data == vqpci->msix_data;
+ }
+ } else {
+ return qpci_io_readb(dev->pdev, dev->addr + QVIRTIO_ISR_STATUS) & 1;
+ }
+}
+
+static bool qvirtio_pci_get_config_isr_status(QVirtioDevice *d)
{
QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
- return qpci_io_readb(dev->pdev, dev->addr + QVIRTIO_ISR_STATUS);
+ uint32_t data;
+
+ if (dev->pdev->msix_enabled) {
+ g_assert_cmpint(dev->config_msix_entry, !=, -1);
+ if (qpci_msix_masked(dev->pdev, dev->config_msix_entry)) {
+ /* No ISR checking should be done if masked, but read anyway */
+ return qpci_msix_pending(dev->pdev, dev->config_msix_entry);
+ } else {
+ data = readl(dev->config_msix_addr);
+ writel(dev->config_msix_addr, 0);
+ return data == dev->config_msix_data;
+ }
+ } else {
+ return qpci_io_readb(dev->pdev, dev->addr + QVIRTIO_ISR_STATUS) & 2;
+ }
}
static void qvirtio_pci_queue_select(QVirtioDevice *d, uint16_t index)
@@ -141,36 +181,38 @@ static QVirtQueue
*qvirtio_pci_virtqueue_setup(QVirtioDevice *d,
uint16_t aux;
uint32_t feat;
uint64_t addr;
- QVirtQueue *vq;
+ QVirtQueuePCI *vqpci;
- vq = g_malloc0(sizeof(*vq));
+ vqpci = g_malloc0(sizeof(*vqpci));
feat = qvirtio_pci_get_guest_features(d);
qvirtio_pci_queue_select(d, index);
- vq->index = index;
- vq->size = qvirtio_pci_get_queue_size(d);
- vq->free_head = 0;
- vq->num_free = vq->size;
- vq->align = QVIRTIO_PCI_ALIGN;
- vq->indirect = (feat & QVIRTIO_F_RING_INDIRECT_DESC) != 0 ? true : false;
+ vqpci->vq.index = index;
+ vqpci->vq.size = qvirtio_pci_get_queue_size(d);
+ vqpci->vq.free_head = 0;
+ vqpci->vq.num_free = vqpci->vq.size;
+ vqpci->vq.align = QVIRTIO_PCI_ALIGN;
+ vqpci->vq.indirect = (feat & QVIRTIO_F_RING_INDIRECT_DESC) != 0;
+
+ vqpci->msix_entry = -1;
+ vqpci->msix_addr = 0;
+ vqpci->msix_data = 0x12345678;
/* Check different than 0 */
- g_assert_cmpint(vq->size, !=, 0);
+ g_assert_cmpint(vqpci->vq.size, !=, 0);
/* Check power of 2 */
- aux = vq->size;
+ aux = vqpci->vq.size;
while ((aux & 1) != 0) {
aux = aux >> 1;
}
g_assert_cmpint(aux, !=, 1);
- addr = guest_alloc(alloc, qvring_size(vq->size, QVIRTIO_PCI_ALIGN));
- qvring_init(alloc, vq, addr);
- qvirtio_pci_set_queue_address(d, vq->desc/4096);
-
- /* TODO: MSI-X configuration */
+ addr = guest_alloc(alloc, qvring_size(vqpci->vq.size, QVIRTIO_PCI_ALIGN));
+ qvring_init(alloc, &vqpci->vq, addr);
+ qvirtio_pci_set_queue_address(d, vqpci->vq.desc/4096);
- return vq;
+ return &vqpci->vq;
}
static void qvirtio_pci_virtqueue_kick(QVirtioDevice *d, QVirtQueue *vq)
@@ -189,7 +231,8 @@ const QVirtioBus qvirtio_pci = {
.get_guest_features = qvirtio_pci_get_guest_features,
.get_status = qvirtio_pci_get_status,
.set_status = qvirtio_pci_set_status,
- .get_isr_status = qvirtio_pci_get_isr_status,
+ .get_queue_isr_status = qvirtio_pci_get_queue_isr_status,
+ .get_config_isr_status = qvirtio_pci_get_config_isr_status,
.queue_select = qvirtio_pci_queue_select,
.get_queue_size = qvirtio_pci_get_queue_size,
.set_queue_address = qvirtio_pci_set_queue_address,
@@ -226,4 +269,68 @@ void qvirtio_pci_device_enable(QVirtioPCIDevice *d)
void qvirtio_pci_device_disable(QVirtioPCIDevice *d)
{
qpci_iounmap(d->pdev, d->addr);
+ d->addr = NULL;
+}
+
+void qvirtqueue_pci_msix_setup(QVirtioPCIDevice *d, QVirtQueuePCI *vqpci,
+ QGuestAllocator *alloc, uint16_t entry)
+{
+ uint16_t vector;
+ uint32_t control;
+ void *addr;
+
+ g_assert(d->pdev->msix_enabled);
+ addr = d->pdev->msix_table + (entry * 16);
+
+ g_assert_cmpint(entry, >=, 0);
+ g_assert_cmpint(entry, <, qpci_msix_table_size(d->pdev));
+ vqpci->msix_entry = entry;
+
+ vqpci->msix_addr = guest_alloc(alloc, 4);
+ qpci_io_writel(d->pdev, addr + PCI_MSIX_ENTRY_LOWER_ADDR,
+ vqpci->msix_addr & ~0UL);
+ qpci_io_writel(d->pdev, addr + PCI_MSIX_ENTRY_UPPER_ADDR,
+ (vqpci->msix_addr >> 32) & ~0UL);
+ qpci_io_writel(d->pdev, addr + PCI_MSIX_ENTRY_DATA, vqpci->msix_data);
+
+ control = qpci_io_readl(d->pdev, addr + PCI_MSIX_ENTRY_VECTOR_CTRL);
+ qpci_io_writel(d->pdev, addr + PCI_MSIX_ENTRY_VECTOR_CTRL,
+ control &
~PCI_MSIX_ENTRY_CTRL_MASKBIT);
+
+ qvirtio_pci_queue_select(&d->vdev, vqpci->vq.index);
+ qpci_io_writew(d->pdev, d->addr + QVIRTIO_MSIX_QUEUE_VECTOR, entry);
+ vector = qpci_io_readw(d->pdev, d->addr + QVIRTIO_MSIX_QUEUE_VECTOR);
+ g_assert_cmphex(vector, !=, VIRTIO_MSI_NO_VECTOR);
+}
+
+void qvirtio_pci_set_msix_configuration_vector(QVirtioPCIDevice *d,
+ QGuestAllocator *alloc, uint16_t entry)
+{
+ uint16_t vector;
+ uint32_t control;
+ void *addr;
+
+ g_assert(d->pdev->msix_enabled);
+ addr = d->pdev->msix_table + (entry * 16);
+
+ g_assert_cmpint(entry, >=, 0);
+ g_assert_cmpint(entry, <, qpci_msix_table_size(d->pdev));
+ d->config_msix_entry = entry;
+
+ d->config_msix_data = 0x12345678;
+ d->config_msix_addr = guest_alloc(alloc, 4);
+
+ qpci_io_writel(d->pdev, addr + PCI_MSIX_ENTRY_LOWER_ADDR,
+ d->config_msix_addr &
~0UL);
+ qpci_io_writel(d->pdev, addr + PCI_MSIX_ENTRY_UPPER_ADDR,
+ (d->config_msix_addr >> 32) &
~0UL);
+ qpci_io_writel(d->pdev, addr + PCI_MSIX_ENTRY_DATA, d->config_msix_data);
+
+ control = qpci_io_readl(d->pdev, addr + PCI_MSIX_ENTRY_VECTOR_CTRL);
+ qpci_io_writel(d->pdev, addr + PCI_MSIX_ENTRY_VECTOR_CTRL,
+ control &
~PCI_MSIX_ENTRY_CTRL_MASKBIT);
+
+ qpci_io_writew(d->pdev, d->addr + QVIRTIO_MSIX_CONF_VECTOR, entry);
+ vector = qpci_io_readw(d->pdev, d->addr + QVIRTIO_MSIX_CONF_VECTOR);
+ g_assert_cmphex(vector, !=, VIRTIO_MSI_NO_VECTOR);
}
diff --git a/tests/libqos/virtio-pci.h b/tests/libqos/virtio-pci.h
index 40bd12d..d6569aa 100644
--- a/tests/libqos/virtio-pci.h
+++ b/tests/libqos/virtio-pci.h
@@ -28,12 +28,24 @@
#define QVIRTIO_PCI_ALIGN 4096
+#define VIRTIO_MSI_NO_VECTOR 0xFFFF
+
typedef struct QVirtioPCIDevice {
QVirtioDevice vdev;
QPCIDevice *pdev;
void *addr;
+ uint16_t config_msix_entry;
+ uint64_t config_msix_addr;
+ uint32_t config_msix_data;
} QVirtioPCIDevice;
+typedef struct QVirtQueuePCI {
+ QVirtQueue vq;
+ uint16_t msix_entry;
+ uint64_t msix_addr;
+ uint32_t msix_data;
+} QVirtQueuePCI;
+
extern const QVirtioBus qvirtio_pci;
void qvirtio_pci_foreach(QPCIBus *bus, uint16_t device_type,
@@ -41,4 +53,9 @@ void qvirtio_pci_foreach(QPCIBus *bus, uint16_t device_type,
QVirtioPCIDevice *qvirtio_pci_device_find(QPCIBus *bus, uint16_t device_type);
void qvirtio_pci_device_enable(QVirtioPCIDevice *d);
void qvirtio_pci_device_disable(QVirtioPCIDevice *d);
+
+void qvirtio_pci_set_msix_configuration_vector(QVirtioPCIDevice *d,
+ QGuestAllocator *alloc, uint16_t
entry);
+void qvirtqueue_pci_msix_setup(QVirtioPCIDevice *d, QVirtQueuePCI *vqpci,
+ QGuestAllocator *alloc, uint16_t
entry);
#endif
diff --git a/tests/libqos/virtio.c b/tests/libqos/virtio.c
index 6310c48..7d1ee7c 100644
--- a/tests/libqos/virtio.c
+++ b/tests/libqos/virtio.c
@@ -78,12 +78,25 @@ void qvirtio_set_driver_ok(const QVirtioBus *bus,
QVirtioDevice *d)
QVIRTIO_DRIVER_OK | QVIRTIO_DRIVER | QVIRTIO_ACKNOWLEDGE);
}
-bool qvirtio_wait_isr(const QVirtioBus *bus, QVirtioDevice *d, uint8_t mask,
+bool qvirtio_wait_queue_isr(const QVirtioBus *bus, QVirtioDevice *d,
+ QVirtQueue *vq, uint64_t timeout)
+{
+ do {
+ clock_step(10);
+ if (bus->get_queue_isr_status(d, vq)) {
+ break; /* It has ended */
+ }
+ } while (--timeout);
+
+ return timeout != 0;
+}
+
+bool qvirtio_wait_config_isr(const QVirtioBus *bus, QVirtioDevice *d,
uint64_t timeout)
{
do {
clock_step(10);
- if (bus->get_isr_status(d) & mask) {
+ if (bus->get_config_isr_status(d)) {
break; /* It has ended */
}
} while (--timeout);
diff --git a/tests/libqos/virtio.h b/tests/libqos/virtio.h
index d0c84a6..5010cfb 100644
--- a/tests/libqos/virtio.h
+++ b/tests/libqos/virtio.h
@@ -109,8 +109,11 @@ typedef struct QVirtioBus {
/* Set status of the device */
void (*set_status)(QVirtioDevice *d, uint8_t status);
- /* Get the ISR status of the device */
- uint8_t (*get_isr_status)(QVirtioDevice *d);
+ /* Get the queue ISR status of the device */
+ bool (*get_queue_isr_status)(QVirtioDevice *d, QVirtQueue *vq);
+
+ /* Get the configuration ISR status of the device */
+ bool (*get_config_isr_status)(QVirtioDevice *d);
/* Select a queue to work on */
void (*queue_select)(QVirtioDevice *d, uint16_t index);
@@ -153,7 +156,9 @@ void qvirtio_set_acknowledge(const QVirtioBus *bus,
QVirtioDevice *d);
void qvirtio_set_driver(const QVirtioBus *bus, QVirtioDevice *d);
void qvirtio_set_driver_ok(const QVirtioBus *bus, QVirtioDevice *d);
-bool qvirtio_wait_isr(const QVirtioBus *bus, QVirtioDevice *d, uint8_t mask,
+bool qvirtio_wait_queue_isr(const QVirtioBus *bus, QVirtioDevice *d,
+ QVirtQueue *vq, uint64_t timeout);
+bool qvirtio_wait_config_isr(const QVirtioBus *bus, QVirtioDevice *d,
uint64_t timeout);
QVirtQueue *qvirtio_virtqueue_setup(const QVirtioBus *bus, QVirtioDevice *d,
QGuestAllocator *alloc, uint16_t
index);
diff --git a/tests/virtio-blk-test.c b/tests/virtio-blk-test.c
index 7269ade..8a8b6ec 100644
--- a/tests/virtio-blk-test.c
+++ b/tests/virtio-blk-test.c
@@ -83,7 +83,7 @@ static void pci_basic(void)
{
QVirtioPCIDevice *dev;
QPCIBus *bus;
- QVirtQueue *vq;
+ QVirtQueuePCI *vqpci;
QGuestAllocator *alloc;
void *addr;
uint64_t w_req;
@@ -119,7 +119,8 @@ static void pci_basic(void)
qvirtio_set_features(&qvirtio_pci, &dev->vdev, features);
alloc = pc_alloc_init();
- vq = qvirtio_virtqueue_setup(&qvirtio_pci, &dev->vdev, alloc, 0);
+ vqpci = (QVirtQueuePCI *)qvirtio_virtqueue_setup(&qvirtio_pci, &dev->vdev,
+ alloc, 0);
qvirtio_set_driver_ok(&qvirtio_pci, &dev->vdev);
@@ -142,11 +143,11 @@ static void pci_basic(void)
g_free(data);
- free_head = qvirtqueue_add(vq, w_req, 528, false, true);
- qvirtqueue_add(vq, w_req+528, 1, true, false);
- qvirtqueue_kick(&qvirtio_pci, &dev->vdev, vq, free_head);
+ free_head = qvirtqueue_add(&vqpci->vq, w_req, 528, false, true);
+ qvirtqueue_add(&vqpci->vq, w_req+528, 1, true, false);
+ qvirtqueue_kick(&qvirtio_pci, &dev->vdev, &vqpci->vq, free_head);
- g_assert(qvirtio_wait_isr(&qvirtio_pci, &dev->vdev, 0x1,
+ g_assert(qvirtio_wait_queue_isr(&qvirtio_pci, &dev->vdev, &vqpci->vq,
QVIRTIO_BLK_TIMEOUT));
status = readb(w_req+528);
g_assert_cmpint(status, ==, 0);
@@ -162,12 +163,12 @@ static void pci_basic(void)
/* r_req->status */
writeb(r_req+528, 0xFF);
- free_head = qvirtqueue_add(vq, r_req, 16, false, true);
- qvirtqueue_add(vq, r_req+16, 513, true, false);
+ free_head = qvirtqueue_add(&vqpci->vq, r_req, 16, false, true);
+ qvirtqueue_add(&vqpci->vq, r_req+16, 513, true, false);
- qvirtqueue_kick(&qvirtio_pci, &dev->vdev, vq, free_head);
+ qvirtqueue_kick(&qvirtio_pci, &dev->vdev, &vqpci->vq, free_head);
- g_assert(qvirtio_wait_isr(&qvirtio_pci, &dev->vdev, 0x1,
+ g_assert(qvirtio_wait_queue_isr(&qvirtio_pci, &dev->vdev, &vqpci->vq,
QVIRTIO_BLK_TIMEOUT));
status = readb(r_req+528);
g_assert_cmpint(status, ==, 0);
@@ -183,13 +184,13 @@ static void pci_basic(void)
/* w_req->status */
writeb(w_req+528, 0xFF);
- free_head = qvirtqueue_add(vq, w_req, 16, false, true);
- qvirtqueue_add(vq, w_req+16, 512, false, true);
- qvirtqueue_add(vq, w_req+528, 1, true, false);
+ free_head = qvirtqueue_add(&vqpci->vq, w_req, 16, false, true);
+ qvirtqueue_add(&vqpci->vq, w_req+16, 512, false, true);
+ qvirtqueue_add(&vqpci->vq, w_req+528, 1, true, false);
- qvirtqueue_kick(&qvirtio_pci, &dev->vdev, vq, free_head);
+ qvirtqueue_kick(&qvirtio_pci, &dev->vdev, &vqpci->vq, free_head);
- g_assert(qvirtio_wait_isr(&qvirtio_pci, &dev->vdev, 0x1,
+ g_assert(qvirtio_wait_queue_isr(&qvirtio_pci, &dev->vdev, &vqpci->vq,
QVIRTIO_BLK_TIMEOUT));
status = readb(w_req+528);
g_assert_cmpint(status, ==, 0);
@@ -199,13 +200,13 @@ static void pci_basic(void)
/* r_req->status */
writeb(r_req+528, 0xFF);
- free_head = qvirtqueue_add(vq, r_req, 16, false, true);
- qvirtqueue_add(vq, r_req+16, 512, true, true);
- qvirtqueue_add(vq, r_req+528, 1, true, false);
+ free_head = qvirtqueue_add(&vqpci->vq, r_req, 16, false, true);
+ qvirtqueue_add(&vqpci->vq, r_req+16, 512, true, true);
+ qvirtqueue_add(&vqpci->vq, r_req+528, 1, true, false);
- qvirtqueue_kick(&qvirtio_pci, &dev->vdev, vq, free_head);
+ qvirtqueue_kick(&qvirtio_pci, &dev->vdev, &vqpci->vq, free_head);
- g_assert(qvirtio_wait_isr(&qvirtio_pci, &dev->vdev, 0x1,
+ g_assert(qvirtio_wait_queue_isr(&qvirtio_pci, &dev->vdev, &vqpci->vq,
QVIRTIO_BLK_TIMEOUT));
status = readb(w_req+528);
g_assert_cmpint(status, ==, 0);
@@ -219,7 +220,7 @@ static void pci_basic(void)
guest_free(alloc, r_req);
/* End test */
- guest_free(alloc, vq->desc);
+ guest_free(alloc, vqpci->vq.desc);
qvirtio_pci_device_disable(dev);
g_free(dev);
test_end();
@@ -229,7 +230,7 @@ static void pci_indirect_config(void)
{
QVirtioPCIDevice *dev;
QPCIBus *bus;
- QVirtQueue *vq;
+ QVirtQueuePCI *vqpci;
QGuestAllocator *alloc;
QVRingIndirectDesc *indirect;
int n_size = TEST_IMAGE_SIZE/2;
@@ -267,14 +268,15 @@ static void pci_indirect_config(void)
qvirtio_set_features(&qvirtio_pci, &dev->vdev, features);
alloc = pc_alloc_init();
- vq = qvirtio_virtqueue_setup(&qvirtio_pci, &dev->vdev, alloc, 0);
+ vqpci = (QVirtQueuePCI *)qvirtio_virtqueue_setup(&qvirtio_pci, &dev->vdev,
+ alloc, 0);
qvirtio_set_driver_ok(&qvirtio_pci, &dev->vdev);
qmp("{ 'execute': 'block_resize', 'arguments': { 'device': 'drive0', "
" 'size': %d } }", n_size);
- g_assert(qvirtio_wait_isr(&qvirtio_pci, &dev->vdev, 0x2,
+ g_assert(qvirtio_wait_config_isr(&qvirtio_pci, &dev->vdev,
QVIRTIO_BLK_TIMEOUT));
capacity = qvirtio_config_readq(&qvirtio_pci, &dev->vdev, addr);
@@ -300,12 +302,12 @@ static void pci_indirect_config(void)
g_free(data);
indirect = qvring_indirect_desc_setup(&dev->vdev, alloc, 2);
- qvring_indirect_desc_add(indirect, w_req, 528, 0);
- qvring_indirect_desc_add(indirect, w_req+528, 1, 1);
- free_head = qvirtqueue_add_indirect(vq, indirect);
- qvirtqueue_kick(&qvirtio_pci, &dev->vdev, vq, free_head);
+ qvring_indirect_desc_add(indirect, w_req, 528, false);
+ qvring_indirect_desc_add(indirect, w_req+528, 1, true);
+ free_head = qvirtqueue_add_indirect(&vqpci->vq, indirect);
+ qvirtqueue_kick(&qvirtio_pci, &dev->vdev, &vqpci->vq, free_head);
- g_assert(qvirtio_wait_isr(&qvirtio_pci, &dev->vdev, 0x1,
+ g_assert(qvirtio_wait_queue_isr(&qvirtio_pci, &dev->vdev, &vqpci->vq,
QVIRTIO_BLK_TIMEOUT));
status = readb(w_req+528);
g_assert_cmpint(status, ==, 0);
@@ -326,10 +328,10 @@ static void pci_indirect_config(void)
indirect = qvring_indirect_desc_setup(&dev->vdev, alloc, 2);
qvring_indirect_desc_add(indirect, r_req, 16, false);
qvring_indirect_desc_add(indirect, r_req+16, 513, true);
- free_head = qvirtqueue_add_indirect(vq, indirect);
- qvirtqueue_kick(&qvirtio_pci, &dev->vdev, vq, free_head);
+ free_head = qvirtqueue_add_indirect(&vqpci->vq, indirect);
+ qvirtqueue_kick(&qvirtio_pci, &dev->vdev, &vqpci->vq, free_head);
- g_assert(qvirtio_wait_isr(&qvirtio_pci, &dev->vdev, 0x1,
+ g_assert(qvirtio_wait_queue_isr(&qvirtio_pci, &dev->vdev, &vqpci->vq,
QVIRTIO_BLK_TIMEOUT));
status = readb(r_req+528);
g_assert_cmpint(status, ==, 0);
@@ -340,13 +342,139 @@ static void pci_indirect_config(void)
memread(r_req+16, data, 512);
g_assert_cmpstr(data, ==, "TEST");
g_free(data);
- g_free(indirect);
guest_free(alloc, w_req);
guest_free(alloc, r_req);
/* End test */
- guest_free(alloc, vq->desc);
+ guest_free(alloc, vqpci->vq.desc);
+ qvirtio_pci_device_disable(dev);
+ g_free(dev);
+ test_end();
+}
+
+static void pci_msix(void)
+{
+ QVirtioPCIDevice *dev;
+ QPCIBus *bus;
+ QVirtQueuePCI *vqpci;
+ QGuestAllocator *alloc;
+ int n_size = TEST_IMAGE_SIZE/2;
+ void *addr;
+ uint64_t w_req;
+ uint64_t r_req;
+ uint64_t capacity;
+ uint32_t features;
+ uint32_t free_head;
+ uint8_t status;
+ char *data;
+
+ bus = test_start();
+ alloc = pc_alloc_init();
+
+ dev = qvirtio_pci_device_find(bus, QVIRTIO_BLK_DEVICE_ID);
+ g_assert(dev != NULL);
+ g_assert_cmphex(dev->vdev.device_type, ==, QVIRTIO_BLK_DEVICE_ID);
+ g_assert_cmphex(dev->pdev->devfn, ==, ((PCI_SLOT << 3) | PCI_FN));
+
+ qvirtio_pci_device_enable(dev);
+ qpci_msix_enable(dev->pdev);
+
+ qvirtio_reset(&qvirtio_pci, &dev->vdev);
+ qvirtio_set_acknowledge(&qvirtio_pci, &dev->vdev);
+ qvirtio_set_driver(&qvirtio_pci, &dev->vdev);
+
+ qvirtio_pci_set_msix_configuration_vector(dev, alloc, 0);
+
+ /* MSI-X is enabled */
+ addr = dev->addr + QVIRTIO_DEVICE_SPECIFIC_MSIX;
+
+ capacity = qvirtio_config_readq(&qvirtio_pci, &dev->vdev, addr);
+ g_assert_cmpint(capacity, ==, TEST_IMAGE_SIZE/512);
+
+ features = qvirtio_get_features(&qvirtio_pci, &dev->vdev);
+ features = features & ~(QVIRTIO_F_BAD_FEATURE |
+ QVIRTIO_F_RING_INDIRECT_DESC |
+ QVIRTIO_F_RING_EVENT_IDX | QVIRTIO_BLK_F_SCSI);
+ qvirtio_set_features(&qvirtio_pci, &dev->vdev, features);
+
+ vqpci = (QVirtQueuePCI *)qvirtio_virtqueue_setup(&qvirtio_pci, &dev->vdev,
+ alloc, 0);
+ qvirtqueue_pci_msix_setup(dev, vqpci, alloc, 1);
+
+ qvirtio_set_driver_ok(&qvirtio_pci, &dev->vdev);
+
+ qmp("{ 'execute': 'block_resize', 'arguments': { 'device': 'drive0', "
+ " 'size': %d } }", n_size);
+
+ g_assert(qvirtio_wait_config_isr(&qvirtio_pci, &dev->vdev,
+ QVIRTIO_BLK_TIMEOUT));
+
+ capacity = qvirtio_config_readq(&qvirtio_pci, &dev->vdev, addr);
+ g_assert_cmpint(capacity, ==, n_size/512);
+
+ /* Write and read with 2 descriptor layout */
+ data = g_malloc0(512);
+ strcpy(data, "TEST");
+
+ /* Write request */
+ w_req = guest_alloc(alloc, sizeof(QVirtioBlkReq)+512);
+ /* w_req->type */
+ writel(w_req, QVIRTIO_BLK_T_OUT);
+ /* w_req->ioprio */
+ writel(w_req+4, 1);
+ /* w_req->sector */
+ writeq(w_req+8, 0);
+ /* w_req->data */
+ memwrite(w_req+16, data, 512);
+ /* w_req->status */
+ writeb(w_req+528, 0xFF);
+
+ g_free(data);
+
+ free_head = qvirtqueue_add(&vqpci->vq, w_req, 528, false, true);
+ qvirtqueue_add(&vqpci->vq, w_req+528, 1, true, false);
+ qvirtqueue_kick(&qvirtio_pci, &dev->vdev, &vqpci->vq, free_head);
+
+ g_assert(qvirtio_wait_queue_isr(&qvirtio_pci, &dev->vdev, &vqpci->vq,
+ QVIRTIO_BLK_TIMEOUT));
+
+ status = readb(w_req+528);
+ g_assert_cmpint(status, ==, 0);
+
+ /* Read request */
+ r_req = guest_alloc(alloc, sizeof(QVirtioBlkReq)+512);
+ /* r_req->type */
+ writel(r_req, QVIRTIO_BLK_T_IN);
+ /* r_req->ioprio */
+ writel(r_req+4, 1);
+ /* r_req->sector */
+ writeq(r_req+8, 0);
+ /* r_req->status */
+ writeb(r_req+528, 0xFF);
+
+ free_head = qvirtqueue_add(&vqpci->vq, r_req, 16, false, true);
+ qvirtqueue_add(&vqpci->vq, r_req+16, 513, true, false);
+
+ qvirtqueue_kick(&qvirtio_pci, &dev->vdev, &vqpci->vq, free_head);
+
+ g_assert(qvirtio_wait_queue_isr(&qvirtio_pci, &dev->vdev, &vqpci->vq,
+ QVIRTIO_BLK_TIMEOUT));
+
+ status = readb(r_req+528);
+ g_assert_cmpint(status, ==, 0);
+
+ data = g_malloc0(512);
+ memread(r_req+16, data, 512);
+ g_assert_cmpstr(data, ==, "TEST");
+ g_free(data);
+
+ guest_free(alloc, w_req);
+ guest_free(alloc, r_req);
+
+ /* End test */
+ guest_free(alloc, vqpci->vq.desc);
+ qpci_msix_disable(dev->pdev);
qvirtio_pci_device_disable(dev);
g_free(dev);
test_end();
@@ -360,6 +488,7 @@ int main(int argc, char **argv)
g_test_add_func("/virtio/blk/pci/basic", pci_basic);
g_test_add_func("/virtio/blk/pci/indirect_config", pci_indirect_config);
+ g_test_add_func("/virtio/blk/pci/msix", pci_msix);
ret = g_test_run();
--
1.7.10.4
