On 08/13/2014 05:07 AM, Bastian Koppelmann wrote: > Add instructions of SRR opcode format. > Add helper for add/sub_ssov. > > Signed-off-by: Bastian Koppelmann <kbast...@mail.uni-paderborn.de> > --- > v4 -> v5: > - gen_sub_d now saves result of substraction into tcg temp to handle ret > = r1 cases. > - gen_mul_i32s now calculates V, SV bits in bit 31. > - SSOV makro now computes V, SV bits in bit 31. > - Negate conditions of 16_SRR_CMOV and 16_SRR_CMOVN insns. > - MOV_AA: Switch r1 and r2 arguments. > > target-tricore/helper.h | 4 ++ > target-tricore/op_helper.c | 43 ++++++++++++ > target-tricore/translate.c | 164 > +++++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 211 insertions(+)
Reviewed-by: Richard Henderson <r...@twiddle.net> r~
