On 25 August 2014 10:16, Sergey Fedorov <serge.f...@gmail.com> wrote:
> On 22.08.2014 14:29, Fabian Aggeler wrote:
>> Preparing for FIQ lines from GIC to CPUs, which is needed for GIC
>> Security Extensions.
>>
>> Signed-off-by: Fabian Aggeler <aggel...@ethz.ch>
>> ---
>> hw/intc/arm_gic.c | 3 +++
>> include/hw/intc/arm_gic_common.h | 1 +
>> 2 files changed, 4 insertions(+)
>>
>> diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
>> index 1532ef9..b27bd0e 100644
>> --- a/hw/intc/arm_gic.c
>> +++ b/hw/intc/arm_gic.c
>> @@ -786,6 +786,9 @@ void gic_init_irqs_and_distributor(GICState *s, int
>> num_irq)
>> for (i = 0; i < NUM_CPU(s); i++) {
>> sysbus_init_irq(sbd, &s->parent_irq[i]);
>> }
>> + for (i = 0; i < NUM_CPU(s); i++) {
>> + sysbus_init_irq(sbd, &s->parent_fiq[i]);
>> + }
>
> Hi Fabian,
>
> I would suggest to provide a way to get a sysbus IRQ/FIQ number for each
> processor, e.g. a dedicated macro. Maybe it could be easier to
> accomplish this by initializing IRQ and FIQ interleaved or by always
> initializing GIC_NCPU IRQs/FIQs.
Using named GPIO registers is the way to go here,
or at least it will be once Peter C's patchset to make
sysbus IRQs just be legacy syntax for GPIOs goes in.
-- PMM
