On 10.09.14 07:03, Pierre Mallard wrote: > This patch series enable floating point instruction in 440x5 CPUs > which have the capabilities to have optional APU FPU. > > 1) Add floating point standard insns flag to 440x5 in case there is an apu > fpu. > 2) Define a new floating point insns flag for operation > previously reserved to 64 bits proc (fcfid, fctid, fctidz) > 3) Apply this new flag to fcfid, fctid, fctidz and move TARGET_PPC64 > restrictions
I've looked through the patches mostly from a stylistic point of view. As for whether the changes are technically correct and fully adhere to the specs, I haven't verified anything and would leave that part to Tom :). Alex
