On 10/08/2014 01:55 PM, Michael S. Tsirkin wrote:
Inline descriptors will amortize the cache miss over 4 descriptors, and will allow the hardware to prefetch, since the descriptors are linear in memory.If descriptors are used in order (as they are with current qemu) then aren't they amortized already?
The descriptors are only in-order for non-zero-copy net. They are out of order for block and zero-copy net.
(also, the guest has to be careful in how it allocates descriptors).
