As per arm specs, if the src and dest register are same, write back
operation is suppressed.
[Specs]
if memop == MemOp_LOAD && wback && n == t && n != 31 then
c = ConstrainUnpredictable();
assert c IN {Constraint_WBSUPPRESS, Constraint_UNKNOWN, Constraint_UNDEF,
Constraint_NOP};
case c of
when Constraint_WBSUPPRESS wback = FALSE; // writeback is suppressed

However, in the code implementation for load / store operation I see that
we do a write back anyhow. [ disas_ldst_reg_imm9]

Can anyone confirm if this is a correct behavior ?

Thanks,
Gaurav

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