* Paolo Bonzini (pbonz...@redhat.com) wrote:
> When the transmit FIFO is emptied or enabled, the transmitter
> hold register is empty. When it is disabled, it is also emptied and
> in addition the previous contents of the transmitter hold register
> are discarded. In either case, the THRE bit in LSR must be set and
> THRI raised.
>
> When the receive FIFO is emptied or enabled, the data ready and break
> bits must be cleared in LSR. Likewise when the receive FIFO is disabled.
>
> Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
> ---
> hw/char/serial.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/hw/char/serial.c b/hw/char/serial.c
> index 4bce268..0a6747c 100644
> --- a/hw/char/serial.c
> +++ b/hw/char/serial.c
> @@ -377,12 +377,15 @@ static void serial_ioport_write(void *opaque, hwaddr
> addr, uint64_t val,
> /* FIFO clear */
>
> if (val & UART_FCR_RFR) {
> + s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
> timer_del(s->fifo_timeout_timer);
> s->timeout_ipending = 0;
> fifo8_reset(&s->recv_fifo);
> }
>
> if (val & UART_FCR_XFR) {
> + s->lsr |= UART_LSR_THRE;
> + s->thr_ipending = 1;
> fifo8_reset(&s->xmit_fifo);
> }
Doesn't that break the assertion you added in patch 2?
i.e. if I write a character, but it can't be sent, so it's added
to the tsr_retry, but before the callback I set FCR_XFR, and that
now sets LSR_THRE, then the callback triggers and it hits the
assert?
Dave
>
> --
> 1.8.3.1
>
>
--
Dr. David Alan Gilbert / dgilb...@redhat.com / Manchester, UK
