On 01/19/2015 11:00 AM, Peter Maydell wrote: > Alternatively (better!), for a lot of the tlb_flush()es triggered > by target-arm code we could be more precise about the affected > mmu_idx values, since the common case is going to be > "NS EL1 did something that needs a TLB flush", and by definition > that can't affect TLB entries for EL2, EL3 or S-EL1/EL0. > > So I think my preference would be to use 7 mmu indexes, > and add a tlb_flush_mmuidx() function. (Assuming I'm > not missing anything that makes that not workable...)
That new interface does seem very reasonable. As to whether you've missed something in the ARM semantics, I guess we'll find out. ;-) r~
