On 01/24/15 10:21, Shannon Zhao wrote:
> This patch series generate seven ACPI v5.1 tables for machine virt on
> ARM.
> The set of generated tables are:
> - RSDP
> - XSDT
> - MADT
> - GTDT
> - FADT
> - FACS
> - DSDT
>
> These tables are created dynamically using the function of
> acpi-build-utils.c, taking into account the needed information passed
> from the virt machine model. When the generation is finalized, it use
> fw_cfg to expose the tables to guest.
>
> This patchset is based on Igor Mammedov's branch which can be found at
> below git tree:
> https://github.com/imammedo/qemu/commits/ASL_API_v2
Awesome! I didn't know you had been coordinating with Igor. This is the
best (or, put differently, "only" :)) possible way forward. Great!
> And this patchset refers to Alexander Spyridakis's patches which are
> sent to qemu-devel mailing list before.
> http://lists.gnu.org/archive/html/qemu-devel/2014-10/msg03987.html
>
> As UEFI (ArmVirtualizationQemu) doesn't support downloading ACPI
> tables over fw_cfg, I just do compile test and start a guest with
> UEFI. But I contacted Laszlo Ersek before, he says that if qemu can
> expose the generated ACPI tables over fw_cfg, he can quickly add
> support in UEFI. So just send this out and make it go forward.
I hope I was quick enough:
- patches: http://thread.gmane.org/gmane.comp.bios.tianocore.devel/12158
- branch: https://github.com/lersek/edk2/commits/armvirt_acpi
- binary: http://people.redhat.com/~lersek/armvirt_acpi/QEMU_EFI.fd
>
> Todo:
> 1) add GPIO controller in virt and expose it through ACPI
> 2) add cpu hotplug support
>
> Any comments are welcome.
I answered with a couple of notes and fixes in the thread. I found those
via testing. I won't offer a code review; I hope you don't mind.
For testing on your end (and for further development) before the edk2
series is applied, you can fetch my patches from github, or even use the
binary I built for you.
Note: the binary includes a very small patch that is not upstream. (Well
it includes some other patches too, but they are not relevant.) This is
it:
> --- a/ArmPlatformPkg/ArmVirtualizationPkg/ArmVirtualizationQemu.dsc
> +++ b/ArmPlatformPkg/ArmVirtualizationPkg/ArmVirtualizationQemu.dsc
> @@ -87,7 +87,7 @@
> gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|FALSE
>
> [PcdsFixedAtBuild.common]
> - gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000004F
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8040004F
>
> gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"QEMU"
It enables the EFI_D_VERBOSE loglevel. The ACPI code logs quite a bit of
info on this loglevel, so if you build an image yourself, be sure to
enable EFI_D_VERBOSE manually. Otherwise you'll only see a part of this
log fragment:
> Loading driver at 0x000BEE66000 EntryPoint=0x000BEE662B0 AcpiPlatformDxe.efi
> InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF BB7BBE98
> ProcessCmdAllocate: File="etc/acpi/rsdp" Alignment=0x10 Zone=2 Size=0x24
> Address=0xB7048000
> ProcessCmdAllocate: File="etc/acpi/tables" Alignment=0x40 Zone=1 Size=0xBC0
> Address=0xB7047000
> ProcessCmdAddChecksum: File="etc/acpi/tables" ResultOffset=0x49 Start=0x40
> Length=0x8F4
> ProcessCmdAddPointer: PointerFile="etc/acpi/tables"
> PointeeFile="etc/acpi/tables" PointerOffset=0x9B8 PointerSize=8
> ProcessCmdAddPointer: PointerFile="etc/acpi/tables"
> PointeeFile="etc/acpi/tables" PointerOffset=0x9C0 PointerSize=8
> ProcessCmdAddChecksum: File="etc/acpi/tables" ResultOffset=0x93D Start=0x934
> Length=0x10C
> ProcessCmdAddChecksum: File="etc/acpi/tables" ResultOffset=0xA49 Start=0xA40
> Length=0xDC
> ProcessCmdAddChecksum: File="etc/acpi/tables" ResultOffset=0xB25 Start=0xB1C
> Length=0x60
> ProcessCmdAddPointer: PointerFile="etc/acpi/tables"
> PointeeFile="etc/acpi/tables" PointerOffset=0xBA0 PointerSize=8
> ProcessCmdAddPointer: PointerFile="etc/acpi/tables"
> PointeeFile="etc/acpi/tables" PointerOffset=0xBA8 PointerSize=8
> ProcessCmdAddPointer: PointerFile="etc/acpi/tables"
> PointeeFile="etc/acpi/tables" PointerOffset=0xBB0 PointerSize=8
> ProcessCmdAddChecksum: File="etc/acpi/tables" ResultOffset=0xB85 Start=0xB7C
> Length=0x44
> ProcessCmdAddPointer: PointerFile="etc/acpi/rsdp"
> PointeeFile="etc/acpi/tables" PointerOffset=0x18 PointerSize=8
> ProcessCmdAddChecksum: File="etc/acpi/rsdp" ResultOffset=0x8 Start=0x0
> Length=0x24
> Process2ndPassCmdAddPointer: checking for ACPI header in "etc/acpi/tables" at
> 0xB7047000 (remaining: 0xBC0): found "FACS" size 0x40
> Process2ndPassCmdAddPointer: checking for ACPI header in "etc/acpi/tables" at
> 0xB7047040 (remaining: 0xB80): found "DSDT" size 0x8F4
> Process2ndPassCmdAddPointer: checking for ACPI header in "etc/acpi/tables" at
> 0xB7047934 (remaining: 0x28C): found "FACP" size 0x10C
> Process2ndPassCmdAddPointer: checking for ACPI header in "etc/acpi/tables" at
> 0xB7047A40 (remaining: 0x180): found "APIC" size 0xDC
> Process2ndPassCmdAddPointer: checking for ACPI header in "etc/acpi/tables" at
> 0xB7047B1C (remaining: 0xA4): found "GTDT" size 0x60
> Process2ndPassCmdAddPointer: checking for ACPI header in "etc/acpi/tables" at
> 0xB7047B7C (remaining: 0x44): found "XSDT" size 0x44
> InstallAllQemuLinkedTables: installed 5 tables
> InstallAllQemuLinkedTables: freeing "etc/acpi/rsdp"
> InstallAllQemuLinkedTables: freeing "etc/acpi/tables"
Before you ask:
- The fact that RSDP is not listed in the log above is not a problem;
it's intentional.
- The fact that XSDT (and RSDT, if it were there) is not installed,
despite being listed, it's intentional too.
- Yes, your code is correct, and you should continue generating those
things; I need them.
The short explanation is that UEFI handles these tables automatically in
"some place", but I still need them "elsewhere".
So that's why 5 tables are installed for OSPM: FACS, DSDT, FACP, ACPI,
GTDT.
Also, I decompiled those tables that were visible under
/sys/firmware/acpi/tables/ inside the guest. Please find them attached.
The FACS won't be there, but I explained that in another email -- the
kernel ignores the FACS because it sees the hw-reduced mode.
Yay! :)
Thanks
Laszlo
/*
* Intel ACPI Component Architecture
* AML Disassembler version 20140926-64 [Sep 29 2014]
* Copyright (c) 2000 - 2014 Intel Corporation
*
* Disassembly of APIC, Sat Jan 24 23:58:20 2015
*
* ACPI Data Table [APIC]
*
* Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
*/
[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)]
[004h 0004 4] Table Length : 000000DC
[008h 0008 1] Revision : 01
[009h 0009 1] Checksum : 34
[00Ah 0010 6] Oem ID : "QEMU "
[010h 0016 8] Oem Table ID : "MACHVIRT"
[018h 0024 4] Oem Revision : 00000001
[01Ch 0028 4] Asl Compiler ID : ""
[020h 0032 4] Asl Compiler Revision : 00000000
[024h 0036 4] Local Apic Address : 08010000
[028h 0040 4] Flags (decoded below) : 00000001
PC-AT Compatibility : 1
[02Ch 0044 1] Subtable Type : 0B [Generic Interrupt Controller]
[02Dh 0045 1] Length : 4C
[02Eh 0046 2] Reserved : 0000
[030h 0048 4] CPU Interface Number : 00000000
[034h 0052 4] Processor UID : 00000000
[038h 0056 4] Flags (decoded below) : 00000001
Processor Enabled : 1
Performance Interrupt Trigger Mode : 0
Virtual GIC Interrupt Trigger Mode : 0
[03Ch 0060 4] Parking Protocol Version : 00000000
[040h 0064 4] Performance Interrupt : 00000000
[044h 0068 8] Parked Address : 0000000000000000
[04Ch 0076 8] Base Address : 0000000008010000
[054h 0084 8] Virtual GIC Base Address : 0000000000000000
[05Ch 0092 8] Hypervisor GIC Base Address : 0000000000000000
[064h 0100 4] Virtual GIC Interrupt : 00000000
[068h 0104 8] Redistributor Base Address : 0000000000000000
[070h 0112 8] ARM MPIDR : 0000000000000000
[078h 0120 1] Subtable Type : 0B [Generic Interrupt Controller]
[079h 0121 1] Length : 4C
[07Ah 0122 2] Reserved : 0000
[07Ch 0124 4] CPU Interface Number : 00000001
[080h 0128 4] Processor UID : 00000001
[084h 0132 4] Flags (decoded below) : 00000001
Processor Enabled : 1
Performance Interrupt Trigger Mode : 0
Virtual GIC Interrupt Trigger Mode : 0
[088h 0136 4] Parking Protocol Version : 00000000
[08Ch 0140 4] Performance Interrupt : 00000000
[090h 0144 8] Parked Address : 0000000000000000
[098h 0152 8] Base Address : 0000000008010000
[0A0h 0160 8] Virtual GIC Base Address : 0000000000000000
[0A8h 0168 8] Hypervisor GIC Base Address : 0000000000000000
[0B0h 0176 4] Virtual GIC Interrupt : 00000000
[0B4h 0180 8] Redistributor Base Address : 0000000000000000
[0BCh 0188 8] ARM MPIDR : 0000000000000001
[0C4h 0196 1] Subtable Type : 0C [Generic Interrupt Distributor]
[0C5h 0197 1] Length : 18
[0C6h 0198 2] Reserved : 0000
[0C8h 0200 4] Local GIC Hardware ID : 00000000
[0CCh 0204 8] Base Address : 0000000008000000
[0D4h 0212 4] Interrupt Base : 00000000
[0D8h 0216 4] Reserved : 00000000
Raw Table Data: Length 220 (0xDC)
0000: 41 50 49 43 DC 00 00 00 01 34 51 45 4D 55 20 20 APIC.....4QEMU
0010: 4D 41 43 48 56 49 52 54 01 00 00 00 00 00 00 00 MACHVIRT........
0020: 00 00 00 00 00 00 01 08 01 00 00 00 0B 4C 00 00 .............L..
0030: 00 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 ................
0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 08 ................
0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
0070: 00 00 00 00 00 00 00 00 0B 4C 00 00 01 00 00 00 .........L......
0080: 01 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 ................
0090: 00 00 00 00 00 00 00 00 00 00 01 08 00 00 00 00 ................
00A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
00B0: 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 ................
00C0: 00 00 00 00 0C 18 00 00 00 00 00 00 00 00 00 08 ................
00D0: 00 00 00 00 00 00 00 00 00 00 00 00 ............
/*
* Intel ACPI Component Architecture
* AML Disassembler version 20140926-64 [Sep 29 2014]
* Copyright (c) 2000 - 2014 Intel Corporation
*
* Disassembly of DSDT, Sat Jan 24 23:58:20 2015
*
* Original Table Header:
* Signature "DSDT"
* Length 0x000008F4 (2292)
* Revision 0x01 **** 32-bit table (V1), no 64-bit math support
* Checksum 0xFE
* OEM ID "QEMU"
* OEM Table ID "MACHVIRT"
* OEM Revision 0x00000001 (1)
* Compiler ID "BXPC"
* Compiler Version 0x00000001 (1)
*/
DefinitionBlock ("DSDT.aml", "DSDT", 1, "QEMU", "MACHVIRT", 0x00000001)
{
Scope (\_SB)
{
Device (CPU0)
{
Name (_HID, "ACPI007") // _HID: Hardware ID
Name (_UID, Zero) // _UID: Unique ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
})
}
Device (CPU1)
{
Name (_HID, "ACPI007") // _HID: Hardware ID
Name (_UID, One) // _UID: Unique ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
})
}
Device (COM0)
{
Name (_HID, "ARMH0011") // _HID: Hardware ID
Name (_UID, Zero) // _UID: Unique ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x09000000, // Address Base
0x00001000, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000021,
}
})
}
Device (RTC0)
{
Name (_HID, "LNRO0013") // _HID: Hardware ID
Name (_UID, Zero) // _UID: Unique ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x09010000, // Address Base
0x00001000, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000022,
}
})
}
Device (FLS0)
{
Name (_HID, "LNRO0015") // _HID: Hardware ID
Name (_UID, Zero) // _UID: Unique ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x00000000, // Address Base
0x08000000, // Address Length
)
})
}
Device (FLS1)
{
Name (_HID, "LNRO0015") // _HID: Hardware ID
Name (_UID, One) // _UID: Unique ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x08000000, // Address Base
0x08000000, // Address Length
)
})
}
Device (VR00)
{
Name (_HID, "LNRO0005") // _HID: Hardware ID
Name (_UID, Zero) // _UID: Unique ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x0A000000, // Address Base
0x00000200, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000030,
}
})
}
Device (VR01)
{
Name (_HID, "LNRO0005") // _HID: Hardware ID
Name (_UID, One) // _UID: Unique ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x0A000200, // Address Base
0x00000200, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000031,
}
})
}
Device (VR02)
{
Name (_HID, "LNRO0005") // _HID: Hardware ID
Name (_UID, 0x02) // _UID: Unique ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x0A000400, // Address Base
0x00000200, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000032,
}
})
}
Device (VR03)
{
Name (_HID, "LNRO0005") // _HID: Hardware ID
Name (_UID, 0x03) // _UID: Unique ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x0A000600, // Address Base
0x00000200, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000033,
}
})
}
Device (VR04)
{
Name (_HID, "LNRO0005") // _HID: Hardware ID
Name (_UID, 0x04) // _UID: Unique ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x0A000800, // Address Base
0x00000200, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000034,
}
})
}
Device (VR05)
{
Name (_HID, "LNRO0005") // _HID: Hardware ID
Name (_UID, 0x05) // _UID: Unique ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x0A000A00, // Address Base
0x00000200, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000035,
}
})
}
Device (VR06)
{
Name (_HID, "LNRO0005") // _HID: Hardware ID
Name (_UID, 0x06) // _UID: Unique ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x0A000C00, // Address Base
0x00000200, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000036,
}
})
}
Device (VR07)
{
Name (_HID, "LNRO0005") // _HID: Hardware ID
Name (_UID, 0x07) // _UID: Unique ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x0A000E00, // Address Base
0x00000200, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000037,
}
})
}
Device (VR08)
{
Name (_HID, "LNRO0005") // _HID: Hardware ID
Name (_UID, 0x08) // _UID: Unique ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x0A001000, // Address Base
0x00000200, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000038,
}
})
}
Device (VR09)
{
Name (_HID, "LNRO0005") // _HID: Hardware ID
Name (_UID, 0x09) // _UID: Unique ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x0A001200, // Address Base
0x00000200, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000039,
}
})
}
Device (VR10)
{
Name (_HID, "LNRO0005") // _HID: Hardware ID
Name (_UID, 0x0A) // _UID: Unique ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x0A001400, // Address Base
0x00000200, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x0000003A,
}
})
}
Device (VR11)
{
Name (_HID, "LNRO0005") // _HID: Hardware ID
Name (_UID, 0x0B) // _UID: Unique ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x0A001600, // Address Base
0x00000200, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x0000003B,
}
})
}
Device (VR12)
{
Name (_HID, "LNRO0005") // _HID: Hardware ID
Name (_UID, 0x0C) // _UID: Unique ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x0A001800, // Address Base
0x00000200, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x0000003C,
}
})
}
Device (VR13)
{
Name (_HID, "LNRO0005") // _HID: Hardware ID
Name (_UID, 0x0D) // _UID: Unique ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x0A001A00, // Address Base
0x00000200, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x0000003D,
}
})
}
Device (VR14)
{
Name (_HID, "LNRO0005") // _HID: Hardware ID
Name (_UID, 0x0E) // _UID: Unique ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x0A001C00, // Address Base
0x00000200, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x0000003E,
}
})
}
Device (VR15)
{
Name (_HID, "LNRO0005") // _HID: Hardware ID
Name (_UID, 0x0F) // _UID: Unique ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x0A001E00, // Address Base
0x00000200, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x0000003F,
}
})
}
Device (VR16)
{
Name (_HID, "LNRO0005") // _HID: Hardware ID
Name (_UID, 0x10) // _UID: Unique ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x0A002000, // Address Base
0x00000200, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000040,
}
})
}
Device (VR17)
{
Name (_HID, "LNRO0005") // _HID: Hardware ID
Name (_UID, 0x11) // _UID: Unique ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x0A002200, // Address Base
0x00000200, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000041,
}
})
}
Device (VR18)
{
Name (_HID, "LNRO0005") // _HID: Hardware ID
Name (_UID, 0x12) // _UID: Unique ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x0A002400, // Address Base
0x00000200, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000042,
}
})
}
Device (VR19)
{
Name (_HID, "LNRO0005") // _HID: Hardware ID
Name (_UID, 0x13) // _UID: Unique ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x0A002600, // Address Base
0x00000200, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000043,
}
})
}
Device (VR20)
{
Name (_HID, "LNRO0005") // _HID: Hardware ID
Name (_UID, 0x14) // _UID: Unique ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x0A002800, // Address Base
0x00000200, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000044,
}
})
}
Device (VR21)
{
Name (_HID, "LNRO0005") // _HID: Hardware ID
Name (_UID, 0x15) // _UID: Unique ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x0A002A00, // Address Base
0x00000200, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000045,
}
})
}
Device (VR22)
{
Name (_HID, "LNRO0005") // _HID: Hardware ID
Name (_UID, 0x16) // _UID: Unique ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x0A002C00, // Address Base
0x00000200, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000046,
}
})
}
Device (VR23)
{
Name (_HID, "LNRO0005") // _HID: Hardware ID
Name (_UID, 0x17) // _UID: Unique ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x0A002E00, // Address Base
0x00000200, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000047,
}
})
}
Device (VR24)
{
Name (_HID, "LNRO0005") // _HID: Hardware ID
Name (_UID, 0x18) // _UID: Unique ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x0A003000, // Address Base
0x00000200, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000048,
}
})
}
Device (VR25)
{
Name (_HID, "LNRO0005") // _HID: Hardware ID
Name (_UID, 0x19) // _UID: Unique ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x0A003200, // Address Base
0x00000200, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000049,
}
})
}
Device (VR26)
{
Name (_HID, "LNRO0005") // _HID: Hardware ID
Name (_UID, 0x1A) // _UID: Unique ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x0A003400, // Address Base
0x00000200, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x0000004A,
}
})
}
Device (VR27)
{
Name (_HID, "LNRO0005") // _HID: Hardware ID
Name (_UID, 0x1B) // _UID: Unique ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x0A003600, // Address Base
0x00000200, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x0000004B,
}
})
}
Device (VR28)
{
Name (_HID, "LNRO0005") // _HID: Hardware ID
Name (_UID, 0x1C) // _UID: Unique ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x0A003800, // Address Base
0x00000200, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x0000004C,
}
})
}
Device (VR29)
{
Name (_HID, "LNRO0005") // _HID: Hardware ID
Name (_UID, 0x1D) // _UID: Unique ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x0A003A00, // Address Base
0x00000200, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x0000004D,
}
})
}
Device (VR30)
{
Name (_HID, "LNRO0005") // _HID: Hardware ID
Name (_UID, 0x1E) // _UID: Unique ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x0A003C00, // Address Base
0x00000200, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x0000004E,
}
})
}
Device (VR31)
{
Name (_HID, "LNRO0005") // _HID: Hardware ID
Name (_UID, 0x1F) // _UID: Unique ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
0x0A003E00, // Address Base
0x00000200, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x0000004F,
}
})
}
}
}
/*
* Intel ACPI Component Architecture
* AML Disassembler version 20140926-64 [Sep 29 2014]
* Copyright (c) 2000 - 2014 Intel Corporation
*
* Disassembly of FACP, Sat Jan 24 23:58:20 2015
*
* ACPI Data Table [FACP]
*
* Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
*/
[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)]
[004h 0004 4] Table Length : 0000010C
[008h 0008 1] Revision : 05
[009h 0009 1] Checksum : B8
[00Ah 0010 6] Oem ID : "QEMU "
[010h 0016 8] Oem Table ID : "MACHVIRT"
[018h 0024 4] Oem Revision : 00000001
[01Ch 0028 4] Asl Compiler ID : ""
[020h 0032 4] Asl Compiler Revision : 00000000
[024h 0036 4] FACS Address : B7046000
[028h 0040 4] DSDT Address : B7045000
[02Ch 0044 1] Model : 00
[02Dh 0045 1] PM Profile : 00 [Unspecified]
[02Eh 0046 2] SCI Interrupt : 0000
[030h 0048 4] SMI Command Port : 00000000
[034h 0052 1] ACPI Enable Value : 00
[035h 0053 1] ACPI Disable Value : 00
[036h 0054 1] S4BIOS Command : 00
[037h 0055 1] P-State Control : 00
[038h 0056 4] PM1A Event Block Address : 00000000
[03Ch 0060 4] PM1B Event Block Address : 00000000
[040h 0064 4] PM1A Control Block Address : 00000000
[044h 0068 4] PM1B Control Block Address : 00000000
[048h 0072 4] PM2 Control Block Address : 00000000
[04Ch 0076 4] PM Timer Block Address : 00000000
[050h 0080 4] GPE0 Block Address : 00000000
[054h 0084 4] GPE1 Block Address : 00000000
[058h 0088 1] PM1 Event Block Length : 00
[059h 0089 1] PM1 Control Block Length : 00
[05Ah 0090 1] PM2 Control Block Length : 00
[05Bh 0091 1] PM Timer Block Length : 00
[05Ch 0092 1] GPE0 Block Length : 00
[05Dh 0093 1] GPE1 Block Length : 00
[05Eh 0094 1] GPE1 Base Offset : 00
[05Fh 0095 1] _CST Support : 00
[060h 0096 2] C2 Latency : 0000
[062h 0098 2] C3 Latency : 0000
[064h 0100 2] CPU Cache Size : 0000
[066h 0102 2] Cache Flush Stride : 0000
[068h 0104 1] Duty Cycle Offset : 00
[069h 0105 1] Duty Cycle Width : 00
[06Ah 0106 1] RTC Day Alarm Index : 00
[06Bh 0107 1] RTC Month Alarm Index : 00
[06Ch 0108 1] RTC Century Index : 00
[06Dh 0109 2] Boot Flags (decoded below) : 0000
Legacy Devices Supported (V2) : 0
8042 Present on ports 60/64 (V2) : 0
VGA Not Present (V4) : 0
MSI Not Supported (V4) : 0
PCIe ASPM Not Supported (V4) : 0
CMOS RTC Not Present (V5) : 0
[06Fh 0111 1] Reserved : 00
[070h 0112 4] Flags (decoded below) : 00100000
WBINVD instruction is operational (V1) : 0
WBINVD flushes all caches (V1) : 0
All CPUs support C1 (V1) : 0
C2 works on MP system (V1) : 0
Control Method Power Button (V1) : 0
Control Method Sleep Button (V1) : 0
RTC wake not in fixed reg space (V1) : 0
RTC can wake system from S4 (V1) : 0
32-bit PM Timer (V1) : 0
Docking Supported (V1) : 0
Reset Register Supported (V2) : 0
Sealed Case (V3) : 0
Headless - No Video (V3) : 0
Use native instr after SLP_TYPx (V3) : 0
PCIEXP_WAK Bits Supported (V4) : 0
Use Platform Timer (V4) : 0
RTC_STS valid on S4 wake (V4) : 0
Remote Power-on capable (V4) : 0
Use APIC Cluster Model (V4) : 0
Use APIC Physical Destination Mode (V4) : 0
Hardware Reduced (V5) : 1
Low Power S0 Idle (V5) : 0
[074h 0116 12] Reset Register : [Generic Address Structure]
[074h 0116 1] Space ID : 00 [SystemMemory]
[075h 0117 1] Bit Width : 00
[076h 0118 1] Bit Offset : 00
[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy]
[078h 0120 8] Address : 0000000000000000
[080h 0128 1] Value to cause reset : 00
[081h 0129 2] ARM Flags (decoded below) : 0003
PSCI Compliant : 1
Must use HVC for PSCI : 1
[083h 0131 1] FADT Minor Revision : 01
[084h 0132 8] FACS Address : 0000000000000000
[08Ch 0140 8] DSDT Address : 00000000B7045000
[094h 0148 12] PM1A Event Block : [Generic Address Structure]
[094h 0148 1] Space ID : 00 [SystemMemory]
[095h 0149 1] Bit Width : 00
[096h 0150 1] Bit Offset : 00
[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy]
[098h 0152 8] Address : 0000000000000000
[0A0h 0160 12] PM1B Event Block : [Generic Address Structure]
[0A0h 0160 1] Space ID : 00 [SystemMemory]
[0A1h 0161 1] Bit Width : 00
[0A2h 0162 1] Bit Offset : 00
[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy]
[0A4h 0164 8] Address : 0000000000000000
[0ACh 0172 12] PM1A Control Block : [Generic Address Structure]
[0ACh 0172 1] Space ID : 00 [SystemMemory]
[0ADh 0173 1] Bit Width : 00
[0AEh 0174 1] Bit Offset : 00
[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy]
[0B0h 0176 8] Address : 0000000000000000
[0B8h 0184 12] PM1B Control Block : [Generic Address Structure]
[0B8h 0184 1] Space ID : 00 [SystemMemory]
[0B9h 0185 1] Bit Width : 00
[0BAh 0186 1] Bit Offset : 00
[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy]
[0BCh 0188 8] Address : 0000000000000000
[0C4h 0196 12] PM2 Control Block : [Generic Address Structure]
[0C4h 0196 1] Space ID : 00 [SystemMemory]
[0C5h 0197 1] Bit Width : 00
[0C6h 0198 1] Bit Offset : 00
[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy]
[0C8h 0200 8] Address : 0000000000000000
[0D0h 0208 12] PM Timer Block : [Generic Address Structure]
[0D0h 0208 1] Space ID : 00 [SystemMemory]
[0D1h 0209 1] Bit Width : 00
[0D2h 0210 1] Bit Offset : 00
[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy]
[0D4h 0212 8] Address : 0000000000000000
[0DCh 0220 12] GPE0 Block : [Generic Address Structure]
[0DCh 0220 1] Space ID : 00 [SystemMemory]
[0DDh 0221 1] Bit Width : 00
[0DEh 0222 1] Bit Offset : 00
[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy]
[0E0h 0224 8] Address : 0000000000000000
[0E8h 0232 12] GPE1 Block : [Generic Address Structure]
[0E8h 0232 1] Space ID : 00 [SystemMemory]
[0E9h 0233 1] Bit Width : 00
[0EAh 0234 1] Bit Offset : 00
[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy]
[0ECh 0236 8] Address : 0000000000000000
[0F4h 0244 12] Sleep Control Register : [Generic Address Structure]
[0F4h 0244 1] Space ID : 00 [SystemMemory]
[0F5h 0245 1] Bit Width : 00
[0F6h 0246 1] Bit Offset : 00
[0F7h 0247 1] Encoded Access Width : 00 [Undefined/Legacy]
[0F8h 0248 8] Address : 0000000000000000
[100h 0256 12] Sleep Status Register : [Generic Address Structure]
[100h 0256 1] Space ID : 00 [SystemMemory]
[101h 0257 1] Bit Width : 00
[102h 0258 1] Bit Offset : 00
[103h 0259 1] Encoded Access Width : 00 [Undefined/Legacy]
[104h 0260 8] Address : 0000000000000000
Raw Table Data: Length 268 (0x10C)
0000: 46 41 43 50 0C 01 00 00 05 B8 51 45 4D 55 20 20 FACP......QEMU
0010: 4D 41 43 48 56 49 52 54 01 00 00 00 00 00 00 00 MACHVIRT........
0020: 00 00 00 00 00 60 04 B7 00 50 04 B7 00 00 00 00 .....`...P......
0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
0070: 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
0080: 00 03 00 01 00 00 00 00 00 00 00 00 00 50 04 B7 .............P..
0090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
00A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
00B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
00E0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
00F0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
0100: 00 00 00 00 00 00 00 00 00 00 00 00 ............
/*
* Intel ACPI Component Architecture
* AML Disassembler version 20140926-64 [Sep 29 2014]
* Copyright (c) 2000 - 2014 Intel Corporation
*
* Disassembly of GTDT, Sat Jan 24 23:58:20 2015
*
* ACPI Data Table [GTDT]
*
* Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
*/
[000h 0000 4] Signature : "GTDT" [Generic Timer Description Table]
[004h 0004 4] Table Length : 00000060
[008h 0008 1] Revision : 01
[009h 0009 1] Checksum : 21
[00Ah 0010 6] Oem ID : "QEMU "
[010h 0016 8] Oem Table ID : "MACHVIRT"
[018h 0024 4] Oem Revision : 00000001
[01Ch 0028 4] Asl Compiler ID : ""
[020h 0032 4] Asl Compiler Revision : 00000000
[024h 0036 8] Counter Block Address : 0000000000000000
[02Ch 0044 4] Reserved : 00000000
[030h 0048 4] Secure EL1 Interrupt : 0000001D
[034h 0052 4] EL1 Flags (decoded below) : 00000001
Trigger Mode : 1
Polarity : 0
Always On : 0
[038h 0056 4] Non-Secure EL1 Interrupt : 0000001E
[03Ch 0060 4] NEL1 Flags (decoded below) : 00000001
Trigger Mode : 1
Polarity : 0
Always On : 0
[040h 0064 4] Virtual Timer Interrupt : 0000001B
[044h 0068 4] VT Flags (decoded below) : 00000001
Trigger Mode : 1
Polarity : 0
Always On : 0
[048h 0072 4] Non-Secure EL2 Interrupt : 0000001A
[04Ch 0076 4] NEL2 Flags (decoded below) : 00000001
Trigger Mode : 1
Polarity : 0
Always On : 0
[050h 0080 8] Counter Read Block Address : 0000000000000000
[058h 0088 4] Platform Timer Count : 00000000
[05Ch 0092 4] Platform Timer Offset : 00000000
Raw Table Data: Length 96 (0x60)
0000: 47 54 44 54 60 00 00 00 01 21 51 45 4D 55 20 20 GTDT`....!QEMU
0010: 4D 41 43 48 56 49 52 54 01 00 00 00 00 00 00 00 MACHVIRT........
0020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
0030: 1D 00 00 00 01 00 00 00 1E 00 00 00 01 00 00 00 ................
0040: 1B 00 00 00 01 00 00 00 1A 00 00 00 01 00 00 00 ................
0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
