On Fri, Feb 20, 2015 at 11:00 AM, Laurent Desnogues <laurent.desnog...@gmail.com> wrote: > On Thu, Feb 19, 2015 at 10:14 PM, Richard Henderson <r...@twiddle.net> wrote: >> While doing the mechanics of a previous patch set converting >> translators to use to TCGLabel pointers, I was reminded of >> several outstanding OPTME comments in the aarch64 translator. >> >> I had started with the csel change, which at first failed and >> took quite some time to debug. See the comment for patch 1. >> >> Since this depends on the outstanding TCGLabel patch set, the >> full tree is available at >> >> git://github.com/rth7680/qemu.git arm-movcond > > Tested on both integer and FP tests. No regression found. > > On the other hand, aarch64-linux-user seems to be significantly > slower on a linux-user test I ran: > > 176.gcc with 166.i > Host: CPU E5-2650 v2 iwth CentOS 6.6 64-bit > time for standard QEMU: ~29s > time for RTH QEMU: ~33s > > Is this expected?
Forget this, I had forgotten to switch to the arm-movcond branch... This patch set breaks fccmp and various integer tests. I'll take a look this afternoon. Laurent > Thanks, > > Laurent > >> >> r~ >> >> >> Richard Henderson (11): >> target-arm: Introduce DisasCompare >> target-arm: Extend NZCF to 64 bits >> target-arm: Handle always condition codes within arm_test_cc >> target-arm: Recognize SXTB, SXTH, SXTW, ASR >> target-arm: Recognize UXTB, UXTH, LSR, LSL >> target-arm: Eliminate unnecessary zero-extend in disas_bitfield >> target-arm: Recognize ROR >> target-arm: Use setcond and movcond for csel >> target-arm: Implement ccmp branchless >> target-arm: Implement fccmp branchless >> target-arm: Implement fcsel with movcond >> >> target-arm/cpu.h | 21 +- >> target-arm/helper.c | 18 +- >> target-arm/translate-a64.c | 688 >> ++++++++++++++++++++++++++------------------- >> target-arm/translate.c | 151 ++++++---- >> target-arm/translate.h | 2 - >> 5 files changed, 524 insertions(+), 356 deletions(-) >> >> -- >> 2.1.0 >> >>