On 16 March 2015 at 11:26, Mikhail Ilyin <m.i...@samsung.com> wrote: > From: Mikhail Ilyin <m.i...@samsung.com> > > At present there are two copies of TPIDRURO register for secure and unsecure > access. TLS is set via a system call __ARM_NR_set_tls and its handler > (cpu_set_tls) always assigns a provided value to unsecure register > tpidrro_el[0]/tpidruro_ns. But during execution for cortex-a15 mrc instruction > returns TLS from secure rigester tpidruro_s which is 0 and causes SIGSEGV. > > Signed-off-by: Mikhail Ilyin <m.i...@samsung.com>
Oops; thanks for this patch. I've applied it to target-arm.next. I took the liberty of rewriting the commit message a bit to better fit in with QEMU's usual style; hope that's OK: ===begin=== linux-user: Access correct register for get/set_tls syscalls on ARM TZ CPUs When support was added for TrustZone to ARM CPU emulation, we failed to correctly update the support for the linux-user implementation of the get/set_tls syscalls. This meant that accesses to the TPIDRURO register via the syscalls were always using the non-secure copy of the register even if native MRC/MCR accesses were using the secure register. This inconsistency caused most binaries to segfault on startup if the CPU type was explicitly set to one of the TZ-enabled ones like cortex-a15. (The default "any" CPU doesn't have TZ enabled and so is not affected.) Use access_secure_reg() to determine whether we should be using the secure or the nonsecure copy of TPIDRURO when emulating these syscalls. ===endit=== -- PMM