Hi Peter and all, Xilinx's next gen SoC has been announced. This series adds a SoC and board.
Series start with addition of ARM cortex A53 support (P1 and P2). The Soc skeleton is then added with GIC, EMACs and UARTs are added. The pre-existing models for GEM and UART are not SoC friendly (no visible state struct), so those are refactored for SoC. Create a model of the EP108 board. Currently this doesn't have any EP108 specific features but is a usable board exposing the user visible features of the raw SoC. changed since v2: Fix CPU child prop adder Add DTS compat string changed since v1: Addressed Alistair review (individual changes on resp. patches) Changed board name to EP108 Changed naming scheme to "zynqmp" / "ZYNQMP" (Michal review) Regards, Peter Peter Crosthwaite (15): target-arm: cpu64: Factor out ARM cortex init target-arm: cpu64: Add support for cortex-a53 arm: Introduce Xilinx ZynqMP SoC arm: xlnx-zynqmp: Add GIC arm: xlnx-zynqmp: Connect CPU Timers to GIC net: cadence_gem: Clean up variable names net: cadence_gem: Split state struct and type into header arm: xilinx-zynqmp: Add GEM support char: cadence_uart: Clean up variable names char: cadence_uart: Split state struct and type into header arm: xilinx-zynqmp: Add UART support arm: Add xlnx-ep108 machine arm: xilinx-ep108: Add external RAM arm: xilinx-ep108: Add bootloading arm: xlnx-zynqmp: Add PSCI setup default-configs/aarch64-softmmu.mak | 2 +- hw/arm/Makefile.objs | 1 + hw/arm/xlnx-ep108.c | 81 +++++++++++++++++ hw/arm/xlnx-zynqmp.c | 168 ++++++++++++++++++++++++++++++++++++ hw/char/cadence_uart.c | 113 ++++++++++-------------- hw/net/cadence_gem.c | 95 ++++++-------------- include/hw/arm/xlnx-zynqmp.h | 29 +++++++ include/hw/char/cadence_uart.h | 35 ++++++++ include/hw/net/cadence_gem.h | 49 +++++++++++ target-arm/cpu64.c | 50 ++++++++--- 10 files changed, 473 insertions(+), 150 deletions(-) create mode 100644 hw/arm/xlnx-ep108.c create mode 100644 hw/arm/xlnx-zynqmp.c create mode 100644 include/hw/arm/xlnx-zynqmp.h create mode 100644 include/hw/char/cadence_uart.h create mode 100644 include/hw/net/cadence_gem.h -- 2.3.1.2.g90df61e.dirty
