On 05/06/2015 08:38 AM, Alvise Rigo wrote: > The purpose of this new bitmap is to flag the memory pages that are in > the middle of LL/SC operations (after a LL, before a SC). > For all these pages, the corresponding TLB entries will be generated > in such a way to force the slow-path. > > The accessors to this bitmap are currently not atomic, but they have to > be so in a real multi-threading TCG. > > Suggested-by: Jani Kokkonen <jani.kokko...@huawei.com> > Suggested-by: Claudio Fontana <claudio.font...@huawei.com> > Signed-off-by: Alvise Rigo <a.r...@virtualopensystems.com> > --- > include/exec/cpu-defs.h | 2 ++ > include/exec/memory.h | 3 ++- > include/exec/ram_addr.h | 19 ++++++++++++++++++- > 3 files changed, 22 insertions(+), 2 deletions(-) > > diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h > index 0ca6f0b..d12cb4c 100644 > --- a/include/exec/cpu-defs.h > +++ b/include/exec/cpu-defs.h > @@ -123,5 +123,7 @@ QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << > CPU_TLB_ENTRY_BITS)); > #define CPU_COMMON \ > /* soft mmu support */ \ > CPU_COMMON_TLB \ > + /* true if in the middle of a LoadLink/StoreConditional */ \ > + bool ll_sc_context; \
Belongs to a different patch? r~
