On 04/12/2010 06:56 PM, Alexander Graf wrote:
For fully system emulation on the other hand I can imagine quite some nice
tricks one could pull.
On PPC hosts you get a huge number of VSIDs that are basically like tags on the
TLB. So if you'd give every x86 page table one VSID you'd potentially have
really great and fast shadow PTEs.
You mean, if you have lots of ppc machines but no x86?
smp would be a problem because of the relaxed memory model (of course
tcg needs a lot of work before it can do smp anyway).
On x86 hosts you can just keep several page tables around. You can then map for
example every combination of guest VSIDs to one page table each.
Yeah.
I'm sure there are similar fun things you can do with the other supported
archs. The hard part is to come up with something generic enough so it works on
all hosts and guests with little effort. Oh well :)
Well, x86 page tables are pretty flexible, the memory model is strict,
the atomics are rich, and you have both unaligned and trapping
accesses. So if you restrict yourself to x86 hosts I think you can do
anything with page size >= 4k.
Run both user and kernel mode in guest user mode, do tcg and mmu in
kernel mode. Should be fun.
--
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