On Mo, 2015-05-11 at 15:49 +0200, Paolo Bonzini wrote: > From: Gerd Hoffmann <kra...@redhat.com>
[ more verbose commit message for squashing in ] The cache bits in ESMRAMC are hardcoded to 1 (=disabled) according to the q35 mch specs. Add and use a define with this default. While being at it also update the SMRAM default to use the name (no code change, just makes things a bit more readable). > Signed-off-by: Gerd Hoffmann <kra...@redhat.com> > Signed-off-by: Paolo Bonzini <pbonz...@redhat.com> > --- > hw/pci-host/q35.c | 1 + > include/hw/pci-host/q35.h | 7 ++++++- > 2 files changed, 7 insertions(+), 1 deletion(-) > > diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c > index 35b89da..8471d7a 100644 > --- a/hw/pci-host/q35.c > +++ b/hw/pci-host/q35.c > @@ -351,6 +351,7 @@ static void mch_reset(DeviceState *qdev) > MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT); > > d->config[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT; > + d->config[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_DEFAULT; > > mch_update(mch); > } > diff --git a/include/hw/pci-host/q35.h b/include/hw/pci-host/q35.h > index 0fff6a2..d3c7bbb 100644 > --- a/include/hw/pci-host/q35.h > +++ b/include/hw/pci-host/q35.h > @@ -128,7 +128,6 @@ typedef struct Q35PCIHost { > > #define MCH_HOST_BRIDGE_SMRAM 0x9d > #define MCH_HOST_BRIDGE_SMRAM_SIZE 2 > -#define MCH_HOST_BRIDGE_SMRAM_DEFAULT ((uint8_t)0x2) > #define MCH_HOST_BRIDGE_SMRAM_D_OPEN ((uint8_t)(1 << 6)) > #define MCH_HOST_BRIDGE_SMRAM_D_CLS ((uint8_t)(1 << 5)) > #define MCH_HOST_BRIDGE_SMRAM_D_LCK ((uint8_t)(1 << 4)) > @@ -139,6 +138,8 @@ typedef struct Q35PCIHost { > #define MCH_HOST_BRIDGE_SMRAM_C_END 0xc0000 > #define MCH_HOST_BRIDGE_SMRAM_C_SIZE 0x20000 > #define MCH_HOST_BRIDGE_UPPER_SYSTEM_BIOS_END 0x100000 > +#define MCH_HOST_BRIDGE_SMRAM_DEFAULT \ > + MCH_HOST_BRIDGE_SMRAM_C_BASE_SEG > > #define MCH_HOST_BRIDGE_ESMRAMC 0x9e > #define MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME ((uint8_t)(1 << 7)) > @@ -151,6 +152,10 @@ typedef struct Q35PCIHost { > #define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_2MB ((uint8_t)(0x1 << 1)) > #define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_8MB ((uint8_t)(0x2 << 1)) > #define MCH_HOST_BRIDGE_ESMRAMC_T_EN ((uint8_t)1) > +#define MCH_HOST_BRIDGE_ESMRAMC_DEFAULT \ > + (MCH_HOST_BRIDGE_ESMRAMC_SM_CACHE | \ > + MCH_HOST_BRIDGE_ESMRAMC_SM_L1 | \ > + MCH_HOST_BRIDGE_ESMRAMC_SM_L2) > > /* D1:F0 PCIE* port*/ > #define MCH_PCIE_DEV 1