Hi Peter,
Thanks for your review.
On 14/05/2015 05:30, Peter Crosthwaite wrote:
On Wed, May 13, 2015 at 12:12 PM, <fred.kon...@greensocs.com> wrote:
From: KONRAD Frederic <fred.kon...@greensocs.com>
This adds the DP and the DPDMA to the Zynq MP.
Signed-off-by: KONRAD Frederic <fred.kon...@greensocs.com>
---
hw/arm/xlnx-zynqmp.c | 23 +++++++++++++++++++++++
include/hw/arm/xlnx-zynqmp.h | 4 ++++
2 files changed, 27 insertions(+)
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index dff6c8a..0eb82fa 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-zynqmp.c
@@ -27,6 +27,10 @@
#define GIC_BASE_ADDR 0xf9000000
#define GIC_DIST_ADDR 0xf9010000
#define GIC_CPU_ADDR 0xf9020000
Blank line.
+#define DP_ADDR 0xfd4a0000
+#define DP_IRQ 113
Blank line
Done, BTW do you agree with the IRQ number?
+#define DPDMA_ADDR 0xfd4c0000
+#define DPDMA_IRQ 116
static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000,
@@ -83,6 +87,16 @@ static void xlnx_zynqmp_init(Object *obj)
object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_CADENCE_UART);
qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default());
}
+
+ object_initialize(&s->dp, sizeof(s->dp), TYPE_XILINX_DP);
+ object_property_add_child(container_get(qdev_get_machine(), "/unattached"),
+ TYPE_XILINX_DP, OBJECT(&s->dp), &error_abort);
+ qdev_set_parent_bus(DEVICE(&s->dp), sysbus_get_default());
+ object_initialize(&s->dpdma, sizeof(s->dpdma), TYPE_XILINX_DPDMA);
+ object_property_add_child(container_get(qdev_get_machine(), "/unattached"),
+ TYPE_XILINX_DPDMA, OBJECT(&s->dpdma),
+ &error_abort);
+ qdev_set_parent_bus(DEVICE(&s->dpdma), sysbus_get_default());
}
static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
@@ -186,6 +200,15 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error
**errp)
sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
gic_spi[uart_intr[i]]);
}
+
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->dp), 0, DP_ADDR);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->dp), 0, gic_spi[DP_IRQ]);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->dpdma), 0, DPDMA_ADDR);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->dpdma), 0, gic_spi[DPDMA_IRQ]);
+ object_property_set_link(OBJECT(&s->dp), OBJECT(&s->dpdma), "dpdma",
+ &error_abort);
Does moving the set_link after the realizes remove the need for the
dummy object_property_add_child?
Regards,
Peter
Ahh good point, I didn't see that object_property_add_child was done in
the realize
step. So yes, you're right. I fixed that.
Thanks,
Fred
+ object_property_set_bool(OBJECT(&s->dp), true, "realized", &err);
+ object_property_set_bool(OBJECT(&s->dpdma), true, "realized", &err);
}
static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data)
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
index 79c2b0b..66ec010 100644
--- a/include/hw/arm/xlnx-zynqmp.h
+++ b/include/hw/arm/xlnx-zynqmp.h
@@ -22,6 +22,8 @@
#include "hw/intc/arm_gic.h"
#include "hw/net/cadence_gem.h"
#include "hw/char/cadence_uart.h"
+#include "hw/dma/xilinx_dpdma.h"
+#include "hw/display/xilinx_dp.h"
#define TYPE_XLNX_ZYNQMP "xlnx,zynqmp"
#define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \
@@ -52,6 +54,8 @@ typedef struct XlnxZynqMPState {
MemoryRegion gic_mr[XLNX_ZYNQMP_GIC_REGIONS][XLNX_ZYNQMP_GIC_ALIASES];
CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS];
CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS];
+ XilinxDPState dp;
+ XilinxDPDMAState dpdma;
} XlnxZynqMPState;
#define XLNX_ZYNQMP_H
--
1.9.0