On 25.05.15 23:05, Aurelien Jarno wrote: > On 2015-05-23 12:33, Richard Henderson wrote: >> On 05/23/2015 12:59 AM, Aurelien Jarno wrote: >>> On 2015-05-21 14:42, Richard Henderson wrote: >>>> Hmm. Seems to be un/under-specified in the PoO. That said, >>> >>> There is a small sentence in the PoO, in chapter "Program Execution", >>> section "Sequence of Storage Reference": >>> >>> It can normally be assumed that the execution of >>> each instruction occurs as an indivisible event. >> >> Ah, I didn't think to look in a different chapter. ;-) >> >>>> It would be nice to know if there ought to be similar up-front access >>>> checking >>>> for STM, to avoid errant partial stores. >>> >>> I have just checked, the same is also true for STM instructions, though >>> it's probably more difficult to fix that in QEMU. Maybe we need a way to >>> check if a load/store will succeed, preferably without using a helper. >> >> I did just suggest a new helper in the "unaligned stores for mips r6" >> thread. Therein we provide a probe_write helper that does assert that the >> given page is writable, or raise the usual exception. It leaves the TLB >> updated, so a subsequent write should take the fast path. > > I guess it would work for softmmu, but not in linux-user mode, though > that's even more a corner case.
For linux-user we could just implement probe as foo = load_x_bytes(addr) store_x_bytes(addr, foo) or can we have write-only maps there? Alex
