On 2015-06-04 17:00, Leon Alrae wrote: > ERETNC is identical to ERET except that an ERETNC will not clear the LLbit > that is set by execution of an LL instruction, and thus when placed between > an LL and SC sequence, will never cause the SC to fail. > > Presence of ERETNC is denoted by the Config5.LLB. > > Signed-off-by: Leon Alrae <leon.al...@imgtec.com> > --- > disas/mips.c | 1 + > target-mips/cpu.h | 1 + > target-mips/helper.h | 1 + > target-mips/op_helper.c | 12 +++++++++++- > target-mips/translate.c | 20 +++++++++++++++----- > target-mips/translate_init.c | 4 +++- > 6 files changed, 32 insertions(+), 7 deletions(-)
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net> As a side note, I have seen that you have added a check for MIPS2 to the ERET instruction. This is correct, but given in practice we don't emulate any MIPS1 CPU, I do wonder if it's not the time to make MIPS2 the basic instruction set and remove all MIPS2 checks. -- Aurelien Jarno GPG: 4096R/1DDD8C9B aurel...@aurel32.net http://www.aurel32.net
