because the capabilities need to be DWORD aligned, so the size
should DWORD aligned too, and then the last capability size can
to be the greatest 0x1000. e.g. if I have a capability starting
4 bytes from the end, 0xFFC. The max size should be 4 bytes,
0x1000 - 0xFFC, not 3 bytes, 0xFFF - 0xFFC.
Signed-off-by: Chen Fan <chen.fan.f...@cn.fujitsu.com>
---
hw/pci/pcie.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c
index 1463e65..6cdd4a1 100644
--- a/hw/pci/pcie.c
+++ b/hw/pci/pcie.c
@@ -595,7 +595,7 @@ void pcie_add_capability(PCIDevice *dev,
assert(offset >= PCI_CONFIG_SPACE_SIZE);
assert(offset < offset + size);
- assert(offset + size < PCIE_CONFIG_SPACE_SIZE);
+ assert(offset + size <= PCIE_CONFIG_SPACE_SIZE);
assert(size >= 8);
assert(pci_is_express(dev));
--
1.9.3
