On Mon, Jun 8, 2015 at 4:31 PM, Peter Crosthwaite <peter.crosthwa...@xilinx.com> wrote: > From: Alistair Francis <alistair.fran...@xilinx.com> > > Originally the use-mmu PVR bits were manually set for each machine. This > is a hassle and difficult to read, instead set them based on the CPU > properties. > > Signed-off-by: Alistair Francis <alistair.fran...@xilinx.com>
Reviewed-by: Peter Crosthwaite <peter.crosthwa...@xilinx.com> > --- > V2: > - Fix up variable name > > target-microblaze/cpu-qom.h | 1 + > target-microblaze/cpu.c | 5 +++-- > target-microblaze/cpu.h | 2 +- > target-microblaze/helper.c | 2 +- > 4 files changed, 6 insertions(+), 4 deletions(-) > > diff --git a/target-microblaze/cpu-qom.h b/target-microblaze/cpu-qom.h > index aa9c032..6bde2e9 100644 > --- a/target-microblaze/cpu-qom.h > +++ b/target-microblaze/cpu-qom.h > @@ -64,6 +64,7 @@ typedef struct MicroBlazeCPU { > bool stackprot; > uint32_t base_vectors; > uint8_t use_fpu; > + bool use_mmu; > } cfg; > > CPUMBState env; > diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c > index a6b6fd7..c4cd68a 100644 > --- a/target-microblaze/cpu.c > +++ b/target-microblaze/cpu.c > @@ -98,7 +98,6 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) > | PVR0_USE_EXC_MASK \ > | PVR0_USE_ICACHE_MASK \ > | PVR0_USE_DCACHE_MASK \ > - | PVR0_USE_MMU \ > | (0xb << 8); > env->pvr.regs[2] = PVR2_D_OPB_MASK \ > | PVR2_D_LMB_MASK \ > @@ -114,7 +113,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error > **errp) > | 0; > > env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) | > - (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0); > + (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) | > + (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0); > > env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) | > (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0); > @@ -168,6 +168,7 @@ static Property mb_properties[] = { > * are enabled > */ > DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.use_fpu, 2), > + DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true), > DEFINE_PROP_END_OF_LIST(), > }; > > diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h > index 60a7500..54e41e8 100644 > --- a/target-microblaze/cpu.h > +++ b/target-microblaze/cpu.h > @@ -122,7 +122,7 @@ typedef struct CPUMBState CPUMBState; > #define PVR0_USE_EXC_MASK 0x04000000 > #define PVR0_USE_ICACHE_MASK 0x02000000 > #define PVR0_USE_DCACHE_MASK 0x01000000 > -#define PVR0_USE_MMU 0x00800000 /* new */ > +#define PVR0_USE_MMU_MASK 0x00800000 > #define PVR0_USE_BTC 0x00400000 > #define PVR0_ENDI 0x00200000 > #define PVR0_FAULT 0x00100000 > diff --git a/target-microblaze/helper.c b/target-microblaze/helper.c > index 69c3252..5156c12 100644 > --- a/target-microblaze/helper.c > +++ b/target-microblaze/helper.c > @@ -56,7 +56,7 @@ int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, > int rw, > int prot; > > mmu_available = 0; > - if (env->pvr.regs[0] & PVR0_USE_MMU) { > + if (cpu->cfg.use_mmu) { > mmu_available = 1; > if ((env->pvr.regs[0] & PVR0_PVR_FULL_MASK) > && (env->pvr.regs[11] & PVR11_USE_MMU) != PVR11_USE_MMU) { > -- > 1.7.1 >