On 12 June 2015 at 20:10, Peter Crosthwaite <peter.crosthwa...@xilinx.com> wrote: > Hi Peter and all, > > This patch series adds ARM Cortex R5 processor support. The PMSAv7 MPU > is implemented. Two R5s are added to the Xilinx ZynqMP SoC.
> Peter Crosthwaite (13): > arm: Do not define TLBTR in PMSA systems > arm: Don't add v7mp registers in MPU systems > arm: helper: Factor out CP regs common to [pv]msa > arm: Refactor get_phys_addr FSR return mechanism > arm: Implement uniprocessor with MP config > arm: Add has-mpu property > target-arm/helper.c: define MPUIR register > arm: helper: rename get_phys_addr_mpu > target-arm: Add registers for PMSAv7 > target-arm: Implement PMSAv7 MPU > target-arm: Add support for Cortex-R5 > arm: xlnx-zynqmp: Preface CPU variables with "apu" > arm: xlnx-zynqmp: Add 2xCortexR5 CPUs Patches 1-6 and 8 all look good to me, so I've added them to target-arm.next in the interest of reducing the size of this series for the next round. I'll send review comments on 9..13 shortly. -- PMM