On 2015-06-29 10:11, Yongbok Kim wrote: > Fix core configuration for MIPS64R6-generic to make it as close as > I6400. > I6400 core has 48-bit of Virtual Address available (SEGBITS). > MIPS SIMD Architecture is available. > Rearrange order of bits to match the specification. > > Signed-off-by: Yongbok Kim <yongbok....@imgtec.com> > --- > target-mips/mips-defs.h | 2 +- > target-mips/translate_init.c | 18 +++++++++--------- > 2 files changed, 10 insertions(+), 10 deletions(-)
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net> That said given we are getting closer to the I6400 CPU model, shouldn't we try to directly model a I6400 core (even if we have to disable some features like IEEE 754-2008 FP) instead of a generic MIPS64R6 core? > diff --git a/target-mips/mips-defs.h b/target-mips/mips-defs.h > index 20aa87c..53b185e 100644 > --- a/target-mips/mips-defs.h > +++ b/target-mips/mips-defs.h > @@ -11,7 +11,7 @@ > #if defined(TARGET_MIPS64) > #define TARGET_LONG_BITS 64 > #define TARGET_PHYS_ADDR_SPACE_BITS 48 > -#define TARGET_VIRT_ADDR_SPACE_BITS 42 > +#define TARGET_VIRT_ADDR_SPACE_BITS 48 > #else > #define TARGET_LONG_BITS 32 > #define TARGET_PHYS_ADDR_SPACE_BITS 40 > diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c > index ddfaff8..9304e74 100644 > --- a/target-mips/translate_init.c > +++ b/target-mips/translate_init.c > @@ -655,14 +655,14 @@ static const mips_def_t mips_defs[] = > (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | > (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), > .CP0_Config2 = MIPS_CONFIG2, > - .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_RXI) | (1 << CP0C3_BP) | > - (1 << CP0C3_BI) | (1 << CP0C3_ULRI) | (1 << > CP0C3_LPA) | > - (1U << CP0C3_M), > - .CP0_Config4 = MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) | > - (3 << CP0C4_IE) | (1 << CP0C4_M), > + .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP) | > + (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) > | > + (1 << CP0C3_RXI) | (1 << CP0C3_LPA), > + .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) | > + (0xfc << CP0C4_KScrExist), > .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_LLB), > - .CP0_Config5_rw_bitmask = (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) | > - (1 << CP0C5_UFE), > + .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) | > + (1 << CP0C5_FRE) | (1 << CP0C5_UFE), > .CP0_LLAddr_rw_bitmask = 0, > .CP0_LLAddr_shift = 0, > .SYNCI_Step = 32, > @@ -674,9 +674,9 @@ static const mips_def_t mips_defs[] = > .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_F64) | (1 << FCR0_L) | > (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) | > (0x00 << FCR0_PRID) | (0x0 << FCR0_REV), > - .SEGBITS = 42, > + .SEGBITS = 48, > .PABITS = 48, > - .insn_flags = CPU_MIPS64R6, > + .insn_flags = CPU_MIPS64R6 | ASE_MSA, > .mmu_type = MMU_TYPE_R4000, > }, > { > -- > 1.7.5.4 > > -- Aurelien Jarno GPG: 4096R/1DDD8C9B aurel...@aurel32.net http://www.aurel32.net