This patch series enables MPU support for Cortex-M3/M4 devices,
based on the existing MPU support for Cortex-R series in QEMU.
The MPU supports a variable number of windows and default to 8, the current
limit on most Cortex-M3/M4 devices. Also, the necessary registers for
exception handling and fault decoding are implemented.
Like on Cortex-R5, the MPU can be turned off by setting "pmsav7-dregion" to
zero.
Alex Zuepke (6):
ARM: add Cortex-M3/M4 exception configuration and status registers
ARM: accessors to Cortex-M3/M4 exception configuration and status
registers
ARM: Cortex-M3/M4: honor STKALIGN in CCR
ARM: Cortex-M3/M4: on exception, set basic bits in exhandling
registers
ARM: enable ARM_FEATURE_MPU for Cortex-M3/M4
ARM: enable PMSAv7-style MPU on Cortex-M3/M4
hw/arm/armv7m.c | 17 ++++-
hw/intc/armv7m_nvic.c | 183 ++++++++++++++++++++++++++++++++++++++++++++++---
target-arm/cpu.c | 2 +
target-arm/cpu.h | 57 +++++++++++++++
target-arm/helper.c | 47 ++++++++++---
target-arm/machine.c | 7 ++
6 files changed, 295 insertions(+), 18 deletions(-)
--
1.7.9.5
