On 2015-07-14 18:17, Paolo Bonzini wrote: > > > On 14/07/2015 17:45, Aurelien Jarno wrote: > > The LWL/LDL instructions mask the GPR with a mask depending on the > > address alignement. It is currently computed by doing: > > > > mask = 0x7fffffffffffffffull >> (t1 ^ 63) > > > > It's simpler to generate it by doing: > > > > mask = (1 << t1) - 1 > > Using ~(-1 << t1) may let you use an ANDN instruction, and is also the > same number of instructions on x86. >
Indeed thanks for the hint. The generated code has the same size, but is one instruction less: mov 0x88(%rsp),%r10 shlx %r10,%rbx,%rbx - mov $0x1,%r11d + mov $0xffffffffffffffff,%r11 shlx %r10,%r11,%r11 - dec %r11 mov 0x18(%r14),%r10 - and %r11,%r10 + andn %r10,%r11,%r10 or %r10,%rbx movslq %ebx,%rbx I'll send a new version of the patch. -- Aurelien Jarno GPG: 4096R/1DDD8C9B aurel...@aurel32.net http://www.aurel32.net
