On 2015-07-15 12:14, Aurelien Jarno wrote: > On 2015-07-15 11:02, Richard Henderson wrote: > > On 07/15/2015 09:06 AM, Aurelien Jarno wrote: > > >On 2015-07-15 09:31, Paolo Bonzini wrote: > > >>Ok, I see your point. If you put it like this :) the fault definitely > > >>lies in the backends. What I'm proposing would be in a new > > >>tcg_reg_alloc_trunc function, and it would require implementing a > > >>non-noop trunc. > > > > > >Why not reusing the existing trunc_shr_i64_i32 op? AFAIU, it has been > > >designed exactly for that. > > > > Indeed. > > > > >Actually I think we should implement the following ops as optional but > > >*real* TCG ops: > > >- trunc_shr_i64_i32 > > >- extu_i32_i64 > > >- ext_i32_i64 > > > > While we could perhaps gain something from the last two, reliably using the > > first is probably the most important. > > > > I've been unable to reproduce the binary in question. I'm curious if > > something as simple as this helps. Alternately, the two hunks might just > > cancel each other out and result in no change. > > No, besides that tcg_assert doesn't exist, it doesn't work, as it is > later optimized out. What I meant is to implement trunc_shr_i64_i32 in > the x86 backend, either as a 32-bit zero extension when count is 0, or a > 64-bit shift zero extended otherwise. > > I think for 2.4 we should go with the ADDR32 way, using the following > kind of patch. It works when %gs is in use, but has to be extended when > it's not in use. The idea is that qemu_ld/st should behave like other > 32-bit ops, that is ignore the high part of the register. >
Oops wrong patch, here is the correct one: diff --git a/tcg/i386/tcg-target.c b/tcg/i386/tcg-target.c index ff4d9cf..e139c44 100644 --- a/tcg/i386/tcg-target.c +++ b/tcg/i386/tcg-target.c @@ -1572,6 +1572,9 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64) if (GUEST_BASE && guest_base_flags) { seg = guest_base_flags; offset = 0; + if (TARGET_LONG_BITS == 32) { + seg |= P_ADDR32; + } } else if (TCG_TARGET_REG_BITS == 64 && offset != GUEST_BASE) { tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_L1, GUEST_BASE); tgen_arithr(s, ARITH_ADD + P_REXW, TCG_REG_L1, base); @@ -1705,6 +1708,9 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64) if (GUEST_BASE && guest_base_flags) { seg = guest_base_flags; offset = 0; + if (TARGET_LONG_BITS == 32) { + seg |= P_ADDR32; + } } else if (TCG_TARGET_REG_BITS == 64 && offset != GUEST_BASE) { tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_L1, GUEST_BASE); tgen_arithr(s, ARITH_ADD + P_REXW, TCG_REG_L1, base); -- Aurelien Jarno GPG: 4096R/1DDD8C9B aurel...@aurel32.net http://www.aurel32.net