On 07/08/2015 19:03, Alvise Rigo wrote: > + > + /* For this vCPU, just update the TLB entry, no need to flush. */ > + env->tlb_table[mmu_idx][index].addr_write |= TLB_EXCL;
Couldn't this vCPU also have two aliasing entries in the TLB? Paolo
On 07/08/2015 19:03, Alvise Rigo wrote: > + > + /* For this vCPU, just update the TLB entry, no need to flush. */ > + env->tlb_table[mmu_idx][index].addr_write |= TLB_EXCL;
Couldn't this vCPU also have two aliasing entries in the TLB? Paolo