On Thu, Jul 30, 2015 at 07:36:35PM +0100, Peter Maydell wrote: > Add the AArch64 registers MAIR_EL3 and TPIDR_EL3, which are the only > two which we had implemented the 32-bit Secure equivalents of but > not the 64-bit Secure versions. > > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.igles...@xilinx.com> > --- > target-arm/helper.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/target-arm/helper.c b/target-arm/helper.c > index 01f0d0d..d59616e 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -1022,6 +1022,10 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { > .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, > .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, > cp15.mair_el[1]), > .resetvalue = 0 }, > + { .name = "MAIR_EL3", .state = ARM_CP_STATE_AA64, > + .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 2, .opc2 = 0, > + .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, > cp15.mair_el[3]), > + .resetvalue = 0 }, > /* For non-long-descriptor page tables these are PRRR and NMRR; > * regardless they still act as reads-as-written for QEMU. > */ > @@ -2790,6 +2794,10 @@ static const ARMCPRegInfo el3_cp_reginfo[] = { > .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 2, > .access = PL3_RW, .accessfn = cptr_access, .resetvalue = 0, > .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[3]) }, > + { .name = "TPIDR_EL3", .state = ARM_CP_STATE_AA64, > + .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 2, > + .access = PL3_RW, .resetvalue = 0, > + .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[3]) }, > REGINFO_SENTINEL > }; > > -- > 1.9.1 >