This is a refresh of a branch I worked on in February, but I don't believe was ever posted. I'm doing so now in order to flush my set of uncommitted branches.
The openrisc target is in terrible shape and, as far as I can tell from the opencores mailing list, no one uses it. The fact that it's missing so many of the instructions in the ISA, so many that we cannot execute the musl libc, is proof of that. This patch set should probably be reviewed and merged, or we should drop the whole target. r~ Richard Henderson (17): target-openrisc: Always enable OPENRISC_DISAS target-openrisc: Streamline arithmetic and OVE target-openrisc: Invert the decoding in dec_calc target-openrisc: Keep SR_F in a separate variable target-openrisc: Use movcond where appropriate target-openrisc: Put SR[OVE] in TB flags target-openrisc: Keep SR_CY and SR_OV in a separate variables target-openrisc: Set flags on helpers target-openrisc: Implement ff1 and fl1 for 64-bit target-openrisc: Represent MACHI:MACLO as a single unit target-openrisc: Rationalize immediate extraction target-openrisc: Enable m[tf]spr from user mode target-openrisc: Enable trap, csync, msync, psync for user mode target-openrisc: Implement muld, muldu, macu, msbu target-openrisc: Fix madd target-openrisc: Write back result before FPE exception target-openrisc: Implement lwa, swa linux-user/main.c | 45 ++ target-openrisc/cpu.c | 1 + target-openrisc/cpu.h | 41 +- target-openrisc/exception_helper.c | 31 + target-openrisc/fpu_helper.c | 286 ++----- target-openrisc/gdbstub.c | 4 +- target-openrisc/helper.h | 42 +- target-openrisc/int_helper.c | 57 +- target-openrisc/interrupt.c | 3 +- target-openrisc/interrupt_helper.c | 3 +- target-openrisc/mmu.c | 1 + target-openrisc/sys_helper.c | 69 +- target-openrisc/translate.c | 1443 ++++++++++++++++-------------------- 13 files changed, 883 insertions(+), 1143 deletions(-) -- 2.4.3