On Thu, Nov 12, 2015 at 09:54:55AM -0800, Peter Crosthwaite wrote: > From: Guenter Roeck <li...@roeck-us.net> > > Add support for the Xilinx XADC core used in Zynq 7000. > > References: > - Zynq-7000 All Programmable SoC Technical Reference Manual > - 7 Series FPGAs and Zynq-7000 All Programmable SoC XADC > Dual 12-Bit 1 MSPS Analog-to-Digital Converter > > Tested with Linux using QEMU machine xilinx-zynq-a9 with devicetree > files zynq-zc702.dtb and zynq-zc706.dtb, and kernel configuration > multi_v7_defconfig. > > Reviewed-by: Alistair Francis <alistair.fran...@xilinx.com> > Signed-off-by: Guenter Roeck <li...@roeck-us.net> > [ PC changes: > * Changed macro names to match TRM where possible > * Made programmers model macro scheme consistent > * Dropped XADC_ZYNQ_ prefix on local macros > * Fix ALM field width > * Update threshold-comparison interrupts in _update_ints() > * factored out DFIFO pushes into helper. Renamed to "push/pop" > * Changed xadc_reg to 10 bits and added OOB check. > * Reduced scope of MCTL reset to just stop channel coms. > * Added dummy read data to write commands > * Changed _ to - seperators in string names and filenames > * Dropped ------------ in header comment > * Catchall'ed _update_ints() in _write handler. > * Minor whitespace changes. > * Use ZYNQ_XADC_FIFO_DEPTH instead of ARRAY_SIZE() > ] > Signed-off-by: Peter Crosthwaite <crosthwaite.pe...@gmail.com>
For v5 (same configuration as above): Tested-by: Guenter Roeck <li...@roeck-us.net>
