On 18/11/2015 18:51, Eduardo Habkost wrote: > Is every CPU supporting PKU guaranteed to have > CPUID.(EAX=0DH,ECX=9):EBX = 0xa80?
We asked Intel a while ago when reorganizing XSAVE support in KVM and QEMU. Unfortunately, Intel is not listing the offsets anymore in the documentation, but they confirmed at the time that offsets won't change. http://lists.xen.org/archives/html/xen-devel/2013-09/msg00484.html is pretty clear in this respect: >> [adding H. Peter Anvin... the context is whether the layout of the >> XSAVE/XRSTOR area is fixed, including the offset of each separate >> Ext_SAVE_Area]. > > It is. > >> So please Intel, pretty please do not modify the XSAVE offsets, and >> clarify this as soon as possible. > > They will not change. > > -hpa This of course doesn't mean that the 0xa80 is correct; it only means that if it is correct, it will always stay correct. :) It makes sense that 0xa80 is correct, since ECX=8 is a supervisor state (thus never saved by XSAVE/XSAVEOPT). The fact that standard format does not account for supervisor states means that supporting supervisor states in KVM might encounter a few small complications. In particular we might have to modify KVM and QEMU to support compacted format in KVM_GET/SET_XSAVE. For now the only supervisor state is just a bunch of MSRs, so it would not be necessary to include it in KVM_GET/SET_XSAVE. Problem averted for now, then. > Where is the PKRU state offset/layout documented? Volume 1 of the SDM, section 13.5.7 ("PKRU State") documents the layout. (Careful: chapter 13 of volume 1 is "Managing State Using the XSAVE Feature Set"; chapter 13 of volume 3 is "System Programming for Instruction Set Extensions and Processor Extended States", and also deals with XSAVE). Paolo
