On 14/12/2015 09:41, Alvise Rigo wrote: > In theory, the provided implementation of TCG LoadLink/StoreConditional > can be used to properly handle atomic instructions on any architecture.
No, _in theory_ this implementation is wrong. If a normal store can make a concurrent LL-SC pair fail, it's provably _impossible_ to handle LL/SC with a wait-free fast path for normal stores. If we decide that it's "good enough", because the race is incredibly rare and doesn't happen anyway for spinlocks, then fine. But it should be represented correctly in the commit messages. Paolo
