Signed-off-by: Paolo Bonzini <pbonz...@redhat.com> --- include/hw/ppc/ppc.h | 36 +++++++++++++++++++++--------------- include/hw/ppc/ppc4xx.h | 17 +++++++++++------ linux-user/main.c | 4 ++-- target-ppc/cpu.h | 10 ++++------ 4 files changed, 38 insertions(+), 29 deletions(-)
diff --git a/include/hw/ppc/ppc.h b/include/hw/ppc/ppc.h index 14efd0c..9eaa410 100644 --- a/include/hw/ppc/ppc.h +++ b/include/hw/ppc/ppc.h @@ -1,8 +1,6 @@ #ifndef HW_PPC_H #define HW_PPC_H 1 -void ppc_set_irq(PowerPCCPU *cpu, int n_IRQ, int level); - /* PowerPC hardware exceptions management helpers */ typedef void (*clk_setup_cb)(void *opaque, uint32_t freq); typedef struct clk_setup_t clk_setup_t; @@ -16,6 +14,9 @@ static inline void clk_setup (clk_setup_t *clk, uint32_t freq) (*clk->cb)(clk->opaque, freq); } +typedef struct ppc_tb_t ppc_tb_t; +typedef struct ppc_dcr_t ppc_dcr_t; + struct ppc_tb_t { /* Time base management */ int64_t tb_offset; /* Compensation */ @@ -48,33 +49,38 @@ struct ppc_tb_t { * the most significant bit is 1. */ +struct CPUPPCState; +struct PowerPCCPU; + uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk, int64_t tb_offset); -clk_setup_cb cpu_ppc_tb_init (CPUPPCState *env, uint32_t freq); +clk_setup_cb cpu_ppc_tb_init (struct CPUPPCState *env, uint32_t freq); /* Embedded PowerPC DCR management */ typedef uint32_t (*dcr_read_cb)(void *opaque, int dcrn); typedef void (*dcr_write_cb)(void *opaque, int dcrn, uint32_t val); -int ppc_dcr_init (CPUPPCState *env, int (*dcr_read_error)(int dcrn), +int ppc_dcr_init (struct CPUPPCState *env, int (*dcr_read_error)(int dcrn), int (*dcr_write_error)(int dcrn)); -int ppc_dcr_register (CPUPPCState *env, int dcrn, void *opaque, +int ppc_dcr_register (struct CPUPPCState *env, int dcrn, void *opaque, dcr_read_cb drc_read, dcr_write_cb dcr_write); -clk_setup_cb ppc_40x_timers_init (CPUPPCState *env, uint32_t freq, +clk_setup_cb ppc_40x_timers_init (struct CPUPPCState *env, uint32_t freq, unsigned int decr_excp); /* Embedded PowerPC reset */ -void ppc40x_core_reset(PowerPCCPU *cpu); -void ppc40x_chip_reset(PowerPCCPU *cpu); -void ppc40x_system_reset(PowerPCCPU *cpu); +void ppc40x_core_reset(struct PowerPCCPU *cpu); +void ppc40x_chip_reset(struct PowerPCCPU *cpu); +void ppc40x_system_reset(struct PowerPCCPU *cpu); void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val); extern CPUWriteMemoryFunc * const PPC_io_write[]; extern CPUReadMemoryFunc * const PPC_io_read[]; void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val); -void ppc40x_irq_init (CPUPPCState *env); -void ppce500_irq_init (CPUPPCState *env); -void ppc6xx_irq_init (CPUPPCState *env); -void ppc970_irq_init (CPUPPCState *env); -void ppcPOWER7_irq_init (CPUPPCState *env); +void ppc_set_irq(struct PowerPCCPU *cpu, int n_IRQ, int level); + +void ppc40x_irq_init (struct CPUPPCState *env); +void ppce500_irq_init (struct CPUPPCState *env); +void ppc6xx_irq_init (struct CPUPPCState *env); +void ppc970_irq_init (struct CPUPPCState *env); +void ppcPOWER7_irq_init (struct CPUPPCState *env); /* PPC machines for OpenBIOS */ enum { @@ -98,6 +104,6 @@ enum { #define PPC_SERIAL_MM_BAUDBASE 399193 /* ppc_booke.c */ -void ppc_booke_timers_init(PowerPCCPU *cpu, uint32_t freq, uint32_t flags); +void ppc_booke_timers_init(struct PowerPCCPU *cpu, uint32_t freq, uint32_t flags); #endif diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h index 91d84ba..f85e183 100644 --- a/include/hw/ppc/ppc4xx.h +++ b/include/hw/ppc/ppc4xx.h @@ -27,10 +27,12 @@ #include "hw/pci/pci.h" +struct PowerPCCPU; + /* PowerPC 4xx core initialization */ -PowerPCCPU *ppc4xx_init(const char *cpu_model, - clk_setup_t *cpu_clk, clk_setup_t *tb_clk, - uint32_t sysclk); +struct PowerPCCPU *ppc4xx_init(const char *cpu_model, + clk_setup_t *cpu_clk, clk_setup_t *tb_clk, + uint32_t sysclk); /* PowerPC 4xx universal interrupt controller */ enum { @@ -38,7 +40,10 @@ enum { PPCUIC_OUTPUT_CINT = 1, PPCUIC_OUTPUT_NB, }; -qemu_irq *ppcuic_init (CPUPPCState *env, qemu_irq *irqs, + +struct CPUPPCState; + +qemu_irq *ppcuic_init (struct CPUPPCState *env, qemu_irq *irqs, uint32_t dcr_base, int has_ssr, int has_vr); ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks, @@ -47,7 +52,7 @@ ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks, hwaddr ram_sizes[], const unsigned int sdram_bank_sizes[]); -void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks, +void ppc4xx_sdram_init (struct CPUPPCState *env, qemu_irq irq, int nbanks, MemoryRegion ram_memories[], hwaddr *ram_bases, hwaddr *ram_sizes, @@ -55,7 +60,7 @@ void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks, #define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost" -PCIBus *ppc4xx_pci_init(CPUPPCState *env, qemu_irq pci_irqs[4], +PCIBus *ppc4xx_pci_init(struct CPUPPCState *env, qemu_irq pci_irqs[4], hwaddr config_space, hwaddr int_ack, hwaddr special_cycle, diff --git a/linux-user/main.c b/linux-user/main.c index 35b021a..2d65f3f 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -1458,12 +1458,12 @@ uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env) } /* XXX: to be fixed */ -int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp) +int ppc_dcr_read (struct ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp) { return -1; } -int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val) +int ppc_dcr_write (struct ppc_dcr_t *dcr_env, int dcrn, uint32_t val) { return -1; } diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 9706000..dd877e6 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -326,9 +326,7 @@ typedef struct opc_handler_t opc_handler_t; /* Types used to describe some PowerPC registers */ typedef struct CPUPPCState CPUPPCState; typedef struct DisasContext DisasContext; -typedef struct ppc_tb_t ppc_tb_t; typedef struct ppc_spr_t ppc_spr_t; -typedef struct ppc_dcr_t ppc_dcr_t; typedef union ppc_avr_t ppc_avr_t; typedef union ppc_tlb_t ppc_tlb_t; @@ -1081,9 +1079,9 @@ struct CPUPPCState { /* Internal devices resources */ /* Time base and decrementer */ - ppc_tb_t *tb_env; + struct ppc_tb_t *tb_env; /* Device control registers */ - ppc_dcr_t *dcr_env; + struct ppc_dcr_t *dcr_env; int dcache_line_size; int icache_line_size; @@ -1263,8 +1261,8 @@ static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn) } /* Device control registers */ -int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp); -int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val); +int ppc_dcr_read (struct ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp); +int ppc_dcr_write (struct ppc_dcr_t *dcr_env, int dcrn, uint32_t val); #define cpu_init(cpu_model) CPU(cpu_ppc_init(cpu_model)) -- 1.8.3.1