On Tue, Feb 2, 2016 at 3:01 PM, Christopher Covington <c...@codeaurora.org> wrote: > Hi Alistair, > > On 02/02/2016 04:22 PM, Alistair Francis wrote: >> On Wed, Aug 5, 2015 at 9:51 AM, Christopher Covington >> <c...@codeaurora.org> wrote: >>> This adds logic to increment PMEVCNTR's based on different event inputs, >>> implements all remaining CP registers, and triggers an interrupt on >>> event overflow. >> >> We (Xilinx) need parts of this patch to avoid kernel panics when >> booting the 4.4 Linux kernel. Have you done any more work on it? If >> you can send out a pach set I'm happy to have a look at it. > > This issue sounds related to Lorenzo Piersali's patch arm64: kernel: fix > PMUv3 registers unconditional access.
Thanks, I found that fix. I still see problems with the pmintenclr_el1 and pmovsclr_el0 registers though. At least in the Xilinx tree. > > As for the status of our TCG PMU patches, unfortunately, last I recall, > I was writing some kvm-unit-tests that Drew wanted me to test against > the KVM PMU, which required real hardware. I got distracted with using > an upstream kernel and a certain distribution on the hardware and have > yet to return. That's unfortunate. Could this patch be split out and applied by itself? Thanks, Alistair > > Cov > > -- > Qualcomm Innovation Center, Inc. > Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, > a Linux Foundation Collaborative Project
