This avoids needing to save state before every FP operation.
Signed-off-by: Richard Henderson <r...@twiddle.net>
---
target-sparc/fop_helper.c | 16 ++++++++++++----
target-sparc/translate.c | 6 +-----
2 files changed, 13 insertions(+), 9 deletions(-)
diff --git a/target-sparc/fop_helper.c b/target-sparc/fop_helper.c
index cdc58ea..02fbf86 100644
--- a/target-sparc/fop_helper.c
+++ b/target-sparc/fop_helper.c
@@ -24,7 +24,7 @@
#define QT0 (env->qt0)
#define QT1 (env->qt1)
-target_ulong helper_check_ieee_exceptions(CPUSPARCState *env)
+static target_ulong do_check_ieee_exceptions(CPUSPARCState *env, uintptr_t ra)
{
target_ulong status = get_float_exception_flags(&env->fp_status);
target_ulong fsr = env->fsr;
@@ -51,12 +51,15 @@ target_ulong helper_check_ieee_exceptions(CPUSPARCState
*env)
}
if ((fsr & FSR_CEXC_MASK) & ((fsr & FSR_TEM_MASK) >> 23)) {
+ CPUState *cs = CPU(sparc_env_get_cpu(env));
+
/* Unmasked exception, generate a trap. Note that while
the helper is marked as NO_WG, we can get away with
writing to cpu state along the exception path, since
TCG generated code will never see the write. */
env->fsr = fsr | FSR_FTT_IEEE_EXCP;
- helper_raise_exception(env, TT_FP_EXCP);
+ cs->exception_index = TT_FP_EXCP;
+ cpu_loop_exit_restore(cs, ra);
} else {
/* Accumulate exceptions */
fsr |= (fsr & FSR_CEXC_MASK) << 5;
@@ -66,6 +69,11 @@ target_ulong helper_check_ieee_exceptions(CPUSPARCState *env)
return fsr;
}
+target_ulong helper_check_ieee_exceptions(CPUSPARCState *env)
+{
+ return do_check_ieee_exceptions(env, GETPC());
+}
+
#define F_HELPER(name, p) void helper_f##name##p(CPUSPARCState *env)
#define F_BINOP(name) \
@@ -262,7 +270,7 @@ void helper_fsqrtq(CPUSPARCState *env)
ret = glue(size, _compare_quiet)(reg1, reg2, \
&env->fp_status); \
} \
- fsr = helper_check_ieee_exceptions(env); \
+ fsr = do_check_ieee_exceptions(env, GETPC()); \
switch (ret) { \
case float_relation_unordered: \
fsr |= (FSR_FCC1 | FSR_FCC0) << FS; \
@@ -293,7 +301,7 @@ void helper_fsqrtq(CPUSPARCState *env)
ret = glue(size, _compare_quiet)(src1, src2, \
&env->fp_status); \
} \
- fsr = helper_check_ieee_exceptions(env); \
+ fsr = do_check_ieee_exceptions(env, GETPC()); \
switch (ret) { \
case float_relation_unordered: \
fsr |= (FSR_FCC1 | FSR_FCC0) << FS; \
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 5874571..688594d 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -3423,7 +3423,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned
int insn)
rs1 = GET_FIELD(insn, 13, 17);
rs2 = GET_FIELD(insn, 27, 31);
xop = GET_FIELD(insn, 18, 26);
- save_state(dc);
+
switch (xop) {
case 0x1: /* fmovs */
cpu_src1_32 = gen_load_fpr_F(dc, rs2);
@@ -3598,7 +3598,6 @@ static void disas_sparc_insn(DisasContext * dc, unsigned
int insn)
rs1 = GET_FIELD(insn, 13, 17);
rs2 = GET_FIELD(insn, 27, 31);
xop = GET_FIELD(insn, 18, 26);
- save_state(dc);
#ifdef TARGET_SPARC64
#define FMOVR(sz) \
@@ -5232,7 +5231,6 @@ static void disas_sparc_insn(DisasContext * dc, unsigned
int insn)
if (gen_trap_ifnofpu(dc)) {
goto jmp_insn;
}
- save_state(dc);
switch (xop) {
case 0x20: /* ldf, load fpreg */
gen_address_mask(dc, cpu_addr);
@@ -5346,7 +5344,6 @@ static void disas_sparc_insn(DisasContext * dc, unsigned
int insn)
if (gen_trap_ifnofpu(dc)) {
goto jmp_insn;
}
- save_state(dc);
switch (xop) {
case 0x24: /* stf, store fpreg */
{
@@ -5405,7 +5402,6 @@ static void disas_sparc_insn(DisasContext * dc, unsigned
int insn)
goto illegal_insn;
}
} else if (xop > 0x33 && xop < 0x3f) {
- save_state(dc);
switch (xop) {
#ifdef TARGET_SPARC64
case 0x34: /* V9 stfa */
--
2.5.0
